74HC154D datasheet(2/22 Pages) PHILIPS

2 / 22 page

2004 Oct 12

Philips Semiconductors

Product speciﬁcation

4-to-16 line decoder/demultiplexer

74HC154; 74HCT154

FEATURES

• 16-line demultiplexing capability

• Decodes 4 binary-coded inputs into one 16 mutually

exclusive outputs

• Complies with JEDEC standard no. 8-1 B

• ESD protection:

HBM EIA/JESD22-A114-B exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V.

• Specified from −40 °C to +85 °C and −40 °C to +125 °C.

DESCRIPTION

The 74HC154; 74HCT154 are high-speed Si-gate CMOS

devices and are pin compatible with low power Schottky

TTL (LSTTL). They are specified in compliance with

JEDEC standard no. 7A.

The 74HC154; 74HCT154 decoders accept four active

HIGH binary address inputs and provide 16 mutually

exclusive active LOW outputs. The two-input enable gate

can be used to strobe the decoder to eliminate the normal

decoding “glitches” on the outputs, or can be used for the

expansion of the decoder.

The enable gate has two ANDed inputs which must be

LOW to enable the outputs.

The 74HC154; 74HCT154 can be used as a 1-to-16

demultiplexer by using one of the enable inputs as the

multiplexed data input.

When the other enable input is LOW, the addressed output

will follow the state of the applied data.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns.

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N+ Σ(CL × VCC2 × fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in Volts;

N = total load switching outputs;

Σ(CL × VCC2 × fo) = sum of the outputs.

2. For 74HC154 the condition is VI = GND to VCC

For 74HCT154 the condition is VI = GND to VCC − 1.5 V.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

74HC154

74HCT154

tPHL/tPLH

propagation delay An, En to Yn

CL = 15 pF; RL =1kΩ;

VCC =5V

input capacitance

3.5

CPD

power dissipation capacitance per gate

notes 1 and 2

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