Block Diagram

20061607

Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

5 - 11

AIN1 to AIN7

Analog inputs. These signals can range from 0V to AV

2NC

This pin is not connected internally, and can be left floating,

or tied to ground.

DIGITAL I/O

16

SCLK

Digital clock input. The range of frequencies for this input is

50 kHz to 8 MHz, with guaranteed performance at 8 MHz.

This clock directly controls the conversion and readout

processes.

15

DOUT

Digital data output. The output samples are clocked out of this

pin on falling edges of the SCLK pin.

14

DIN

Digital data input. The ADC78H89’s Control Register is

loaded through this pin on rising edges of the SCLK pin.

1CS

Chip select. On the falling edge of CS, a conversion process

begins. Conversions continue as long as CS is held low.

POWER SUPPLY

3AV

DD

Positive analog supply pin. This pin should be connected to a

quiet +2.7V to +5.25V source and bypassed to GND with 0.1

µF ceramic monolithic and 1 µF tantalum capacitors located

within 1 cm of the power pin.

13

DV

DD

Positive digital supply pin. This pin should be connected to a

+2.7V to AV

ceramic monolithic capacitor located within 1 cm of the power

pin.

4, 12

GND

The ground return for both analog and digital supplies. These

pins are tied directly together internally, so must be connected

to the same potential. If any potential exists across these

pins, large currents will flow through the device.

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