AT45DB321C datasheet(20/37 Pages) ATMEL

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AT45DB321C [Preliminary]

3387B–DFLSH–9/04

Input Test Waveforms and Measurement Levels

tR, tF < 2 ns (10% to 90%)

Output Test Load

AC Waveforms

Four different timing waveforms are shown below. Waveform 1 shows the SCK signal

being low when CS makes a high-to-low transition, and waveform 2 shows the SCK sig-

nal being high when CS makes a high-to-low transition. In both cases, output SO

becomes valid while the SCK signal is still low (SCK low time is specified as t

WL). Timing

waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 33 MHz

and are compatible with SPI Mode 0 and SPI Mode 3 respectively. Waveforms 1 and 2

are also compatible with inactive clock polarity low and inactive clock polarity high, since

the maximum specified frequency in that case is 33 MHz.

Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial inter-

face. These are similar to waveform 1 and waveform 2, except that output SO is not

restricted to become valid during the t

WL period. These timing waveforms are valid over

the full frequency range (maximum frequency = 40 MHz) of the RapidS serial case.

DRIVING

LEVELS

MEASUREMENT

LEVEL

1.5V

3.0V

DEVICE

UNDER

TEST

30 pF

AT45DB321C 데이터시트(PDF) 20 Page - ATMEL Corporation