LTM4645 datasheet(20/34 Pages) LINER

20 / 34 page

LTM4645

4645f

For more information www.linear.com/LTM4645

applicaTions inForMaTion

A graphical representation of the aforementioned ther-

mal resistances is given in Figure 9; blue resistances are

contained within the µModule regulator, whereas green

resistances are external to the µModule package. As a

practical matter, it should be clear to the reader that no

individual or sub-group of the four thermal resistance

parameters defined by JESD 51-12 or provided in the

Pin Configuration section replicates or conveys normal

operating conditions of a µModule regulator. For example,

in normal board-mounted applications, never does 100%

of the device’s total power loss (heat) thermally conduct

exclusively through the top or exclusively through bot-

tom of the µModule package—as the standard defines

for

θJCtop and θJCbottom, respectively. In practice, power

loss is thermally dissipated in both directions away from

the package—granted, in the absence of a heat sink and

airflow, a majority of the heat flow is into the board.

Within the LTM4645, be aware there are multiple power

devices and components dissipating power, with a con-

sequence that the thermal resistances relative to different

junctions of components or die are not exactly linear with

respect to total package power loss. To reconcile this

4645 F09

µMODULE DEVICE

JUNCTION-TO-CASE (TOP)

RESISTANCE

JUNCTION-TO-BOARD RESISTANCE

JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

CASE (TOP)-TO-AMBIENT

RESISTANCE

BOARD-TO-AMBIENT

RESISTANCE

JUNCTION-TO-CASE

(BOTTOM) RESISTANCE

JUNCTION

CASE (BOTTOM)-TO-BOARD

RESISTANCE

Figure 9. Graphical Representation of JESD51-12 Thermal Coefficients

complicationwithoutsacrificingmodelingsimplicity—but

alsonotignoringpracticalrealities—anapproachhasbeen

taken using FEA software modeling along with laboratory

testing in a controlled-environment chamber to reason-

ably define and correlate the thermal resistance values

supplied in this data sheet: (1) Initially, FEA software is

used to accurately build the mechanical geometry of the

LTM4645 and the specified PCB with all of the correct

materialcoefficientsalongwithaccuratepowerlosssource

definitions; (2) this model simulates a software-defined

JEDEC environment consistent with JESD51-12 to predict

power loss heat flow and temperature readings at different

interfaces that enable the calculation of the JEDEC-defined

thermal resistance values; (3) the model and FEA software

isusedtoevaluatetheLTM4645withheatsinkandairflow;

(4) having solved for and analyzed these thermal resis-

tance values and simulated various operating conditions

in the software model, a thorough laboratory evaluation

replicates the simulated conditions with thermocouples

within a controlled-environment chamber while operat-

ing the device at the same power loss as that which was

simulated. The outcome of this process and due diligence

yields the set of derating curves shown in this data sheet.

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