When the Deserializer’s PD* signal is de-asserted, the WC

output will power up and initialize the serializer and start

transmitting the clock reference. Once the Serializer re-

ceived the clock, it waits seven cycles, and then outputs the

clock signal. Seven cycles later, the Serializer’s PLL will

begin to lock if PCLK is present.

When the Deserializer’s PD* signal is asserted, the WC

signal is turned off.

MISC. Definitions:

Bus States:

Logic Low — 5Idata flowing from the Receiver to the

Driver

Logic High — Idata flowing from the Receiver to the Driver

Power Off —

No Current flowing in the interconnect

Signals & Nomenclature:

MD = MPL Data Signal, subscript denotes source, m =

master, s = slave

MC = MPL Clock Signal

WC = MPL WhisperClock Signal

* =

Active Low Signal

20091609

FIGURE 11. Active to Sleep

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