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TLE94004EP 데이터시트(PDF) 4 Page - Infineon Technologies AG |
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TLE94004EP 데이터시트(HTML) 4 Page - Infineon Technologies AG |
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4 / 35 page ![]() Datasheet 4 1.0 2017-12-07 TLE94004EP Pin Configuration 1 Pin Configuration 1.1 Pin Assignment Figure 1 Pin Configuration TLE94004EP with direct interface 1.2 Pin Definitions and Functions Pin Symbol Function 1 IN 1 Direct input control for power half-bridge 1 2 IN 2 Direct input control for power half-bridge 2 3 IN 3 Direct input control for power half-bridge 3 4 IN 4 Direct input control for power half-bridge 4 5 VS Main supply voltage for power half bridges. 6OUT 3 Power half-bridge 3 7OUT 1 Power half-bridge 1 8GND Ground 9OUT 2 Power half-bridge 2 10 OUT 4 Power half-bridge 4 11 EN1 Enable input for Half-bridges 1/2 with internal pull-down 12 EN2 Enable input for Half-bridges 3/4 with internal pull-down 13 EF Error Flag 14 VDD Logic supply voltage EDP - Exposed Die Pad; For cooling and EMC purposes only - not usable as electrical ground. Electrical ground must be provided by pins 8. 1) 1) The exposed die pad at the bottom of the package allows better heat dissipation from the device via the PCB. The exposed pad (EP) must be either left open or connected to GND. It is recommended to connect EP to GND for best EMC and thermal performance. IN 1 VDD IN 2 IN 3 IN 4 VS OUT 3 OUT 1 EN2 EN1 EF OUT 4 OUT 2 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 |
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