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LTC6253 데이터시트(PDF) 24 Page - Linear Technology

부품명 LTC6253
상세설명  280MHz, 2.9ns Comparator Family with Rail-to-Rail Inputs and CMOS Outputs
PDF  30 Pages
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제조업체  LINER [Linear Technology]
홈페이지  http://www.linear.com
Logo LINER - Linear Technology

LTC6253 데이터시트(HTML) 24 Page - Linear Technology

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LTC6752/LTC6752-1/
LTC6752-2/LTC6752-3/
LTC6752-4
24
6752fc
For more information www.linear.com/LTC6752
Typical applicaTions
Common Mode Rejecting Line Receiver
Differential electrical signals being transmitted over long
cables are often attenuated. Electrical noise on the cables
can take the form of common mode signals.
The LTC6752 comparators can be used to retrieve attenu-
ated differential signals that have been corrupted by high
frequency common mode noise, as shown in Figure 14.
Figure 15 shows an LTC6752-2 retrieving a 200MHz,
200mVP-Pdifferentialinputsignalthathas2.5Vofrandom,
commonmodenoisesuperimposedonit. Theinputsupply
(VCC) used was 5V and the output supply used was 2.7V.
A small amount of modulation is seen at the output due
to a small amount of differential modulation at the inputs,
whichcausescycletocyclevariationsinpropagationdelay.
Fast Event Capture
The circuit shown in Figure 16 can be used to capture
small and fast events. The comparator output is used to
signal the latch pin and hold the output in the HIGH state.
The circuit will reset when the RESET line is low. An open
drain 1.5ns NAND gate is used to both invert the output
signal and is used to MUX in the RESET line from the
supervising circuit. One important feature of the NAND is
that it is open drain which allows the comparator to use
either its default 5mV of hysteresis or a user programmed
hysteresis.Thelatchrecoverytimeofthiscircuitisroughly
210nsandisdominatedbythetimeconstantcreatedbythe
capacitance seen at the output of the NAND gate and the
20k series resistance of the LE/HYST pin. The waveforms
are shown in Figure 17.
Figure 14
Figure 15
–
+
VCC = 5V
VDD = 2.7V
Q
6752 F14
SMALL DIFFERENTIAL SIGNAL WITH
LARGE COMMON MODE COMPONENT
VEE
+IN
–IN
LTC6752-2
500mV/DIV
–IN +IN
Q
50ns/DIV
6752 F15
Figure 16
Figure 17
500mV/DIV
50ns/DIV
6752 F17
RESET
INPUT
REF
OUT
3.3V
6752 F16
–
+
VCC
LTC6752-2
VDD
VEE
LE/HYST
SHDN
Q
2.2F
0.1F
0.1F
200
182k
EVENT IN
50mV, 10ns
INPUT
RESET
3.3V
REF
NXP 74LVC1G38
OUT



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