EL7155CSZ datasheet(8/10 Pages) RENESAS

8 / 10 page

EL7155

FN7279 Rev 3.00

Page 8 of 10

October 24, 2014

Applications Information

Product Description

The EL7155 is a high performance 40MHz pin driver. It contains

two analog switches connecting VH to OUTH and VL to OUTL.

Depending on the value of the IN pin, one of the two switches will

be closed and the other switch open. An output enable (OE) is

also supplied, which opens both switches simultaneously.

Due to the topology of the EL7155, VL should always be

connected to a voltage equal to or lower than GND. VH can be

connected to any voltage between VL and the positive supply,

VS+.

The EL7155 is available in the 8 Ld SOIC package. Application

dependent power dissipation should be calculated to ensure that

the maximum junction temperature isn’t violated.

3-state Operation

When the OE pin is low, the output is 3-state (floating.) The

disabled output voltage is the parasitic capacitance’s voltage. It

can be any voltage between VH and VL, depending on the

previous state. At 3-state, the output voltage can be driven to any

voltage between VH and VL. The output voltage can’t be driven

higher than VH or lower than VL since the body diode at the

output stage will turn on.

Supply Voltage Range and Input

Compatibility

The EL7155 is designed for operation on supplies from 5V to 15V

(4.5V to 16.5V maximum). Table 2 on page 7 shows the

specifications for the relationship between the VS+, VH, VL, and

GND pins.

All input pins are compatible with both 3V and 5V CMOS signals.

With a positive supply (VS+) of 5V, the EL7155 is also compatible

with TTL inputs.

Power Supply Bypassing

When using the EL7155, it is very important to use adequate

power supply bypassing. The high switching currents developed

by the EL7155 necessitate the use of a bypass capacitor

between the VS+ and GND pins. It is recommended that a 2.2µF

tantalum capacitor be used in parallel with a 0.1µF

low-inductance ceramic MLC capacitor. These should be placed

as close to the supply pins as possible. It is also recommended

that the VH and VL pins have some level of bypassing, especially

if the EL7155 is driving highly capacitive loads.

Power Dissipation Calculation

When switching at high speeds, or driving heavy loads, the

EL7155 drive capability is limited by the rise in die temperature

brought about by internal power dissipation. For reliable

operation die temperature must be kept below TJMAX (+125°C).

It is necessary to calculate the power dissipation for a given

application prior to selecting the package type.

Power dissipation may be calculated:

where:

VS is the total power supply to the EL7155 (from VS+ to GND)

VOUT is the swing on the output (VH - VL)

CL is the load capacitance

CINT is the internal load capacitance (100pF max)

IS is the quiescent supply current (3mA max)

f is frequency

Having obtained the application’s power dissipation, a maximum

package thermal coefficient may be determined, to maintain the

internal die temperature below TJMAX:

where:

TJMAX is the maximum junction temperature (+125°C)

TMAX is the maximum operating temperature

PD is the power dissipation calculated above

JA thermal resistance on junction to ambient

JA is 160°C/W for the SO8 package when using a standard

JEDEC JESD51-3 single-layer test board. If TJMAX is greater than

+125°C when calculated using the Equation 2, then one of the

following actions must be taken:

1. Reduce

JA the system by designing more heatsinking into

the PCB (as compared to the standard JEDEC JESD51-3).

2. Derate the application either by reducing the switching

frequency, the capacitive load, or the maximum operating

(ambient) temperature (TMAX).



IS CINT







VOUT





(EQ. 1)



TJMAX



TMAX

–

----------------------------------------------

(EQ. 2)

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