MP6501A – 35V, 2.5A MICROSTEPPING MOTOR DRIVER WITH INTEGRATED FETS

MP6501A Rev. 1.11

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12

8/22/2016

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resolution and control. Full step has four states

with each motor winding driven with either

70.7% maximum positive current or 70.7%

maximum negative current. This provides four

steps per electrical rotation. Half step creates 8

steps per electrical rotation. Quarter- and

eighth- step provide 16 and 32 steps per

rotation respectively. Table 2 shows the relative

current level sequence for different settings of

MSx.

Table 1: Stepping Format

MS3

MS2

MS1

STEP MODE

L

L

L

Full Step

L

L

H

Half Step

L

H

L

Quarter Step

L

H

H

Eighth Step

H

L

L

Reserved

H

L

H

Reserved

H

H

L

Reserved

H

H

H

Reserved

Decay Modes

During the PWM off time, the output current

decay can operate in slow, fast, or mixed decay,

depending on the voltage level at the MDS

input, and any current change commanded by a

STEP transition.

If the voltage on the MDS input pin is less than

2.5V, then mixed decay mode with adjustable

fast decay ratio is selected. The time that the

device operates in fast decay is approximated

by:

OFF

mds

FD

t

V

V

t







4

.

0

)

(

switch to slow decay mode for the remainder of

the constant off-time period. Note that if the

MDS pin is set to 0V (connected to ground),

slow decay is used for the entire off time.

If the voltage at the MDS input is greater than

2.8 V, then automatic decay mode is selected.

In automatic decay mode, if the commanded

current level is equal or higher than the level at

the previous step, then slow decay is selected;

if current level is lower than previous level, then

mixed decay with fixed 30% fast decay ratio is

selected.

nRSET, nSLEEP, and nENBL Operation

When the nRSET pin is set to low, the

excitation position is forcibly set to the home

position. The step input signal is ignored during

this period.

Driving nSLEEP low will put the device into a

low power sleep state. In this state, the gate

drive charge pump and 3P3VOUT regulator is

stopped; all the internal circuits and H-bridge

outputs are disabled. All inputs are ignored

when nSLEEP is active low. When waking up

from sleep mode, some time (approximately 1

ms) needs to pass before issuing a STEP

command, to allow the internal circuitry to

stabilize.

The nENBL pin is used to control the output

drivers. When nENBL is low, the output H-

bridge outputs are enabled, and rising edges on

the STEP pin are recognized. When nENBL is

high, the H-bridge outputs are disabled, and the

STEP input is ignored.

Blanking Time

There is usually a current spike during the

switching transition due to the body diode’s

reverse-recovery current or the distributed

inductance or capacitance. This current spike

requires filtering to prevent it from erroneously

shutting down the high-side MOSFET. An

output of the current sense comparator when

the outputs are switched, which is also the

minimum on time for high-side MOSFET.

In automatic decay mode, if the current limit is

reached within the blanking time, the mixed

decay with 30% fast decay ratio is performed

after the blanking time.

Charge Pump

The MP6501A integrates an internal charge

pump to generate gate drive voltage for the

high-side

MOSFETs.

The

charge

pump

requires a 100nF ceramic capacitor (rated for at

least the voltage applied to VIN) to be

connected between the CPA and CPB pins,

and a 1uF 16V ceramic capacitor connected

between VCP and VIN.

Fault

MP6501A provides a nFAULT pin, which

reports the system if the protection circuit

operates by detecting a fault condition such as

OCP, OTP and OVP. This pin is of the open-

drain output type and will be driven low once