AC207-DS04-405-R datasheet(32/60 Pages) BOARDCOM

32 / 60 page

AC207

Preliminary Data Sheet

07/08/02

B roa dcom

Page 22 PHY Registers

Document

AC207-DS04-405-R

PHY REGISTERS

The following registers are defined for each PHY port. The base addresses of PHY 1 to PHY 8 are 0, 1, 2, 3, 4, 5, 6, and 7

respectively.

PHY CONFIGURATION REGISTER

Table 19: PHY Configuration Register 0

Bit

Name

Definition

Mode

Default

0.15

Reset

1 = PHY reset

This bit is self-clearing.

RW/SC

0.14

Loopback

1 = Loopback mode, which internally loop the transmit of AC207 to

its receive, thus it will ignore all the activity on the cable media.

0 = Normal operation.

0.13

Speed select

1 = 100 Mbps

0 = 10 Mbps. This bit will be ignored if auto-negotiation is enabled.

It will no longer reflect auto-negotiation result.

0.12

Auto-neg enable

1 = Enable auto-negotiate process (overrides 0.13 and 0.8)

0 = Disable auto-negotiate process.

In force mode, speed is selected via bit 0.13.

0.11

Power-down

1 = Power-down mode, which puts AC207 in low-power stand-by

mode, which only reacts to access transaction.

0 = Normal operation.

0.10

Isolate

1 = Electrical isolation of PHY from MII and cable media.

0 = Normal operation.

0.9

Restart

auto-negotiation

1 = Restart auto-negotiation process.

0 = Normal operation.

RW/ SC

0.8

Duplex mode

1 = Full-duplex.

0 = Half-duplex.

Full-duplex is not supported on this chip. It will no longer reflect

auto-negotiation result.

0.7

Collision test

1 = Enable collision test, which issues the COL signal in response

to the assertion of TX_EN signal.

0 = Disable COL test.

0.6:0

Reserved

000000

AC207-DS04-405-R 데이터시트(PDF) 32 Page - Broadcom Corporation.

AC207-DS04-405-R 데이터시트(HTML) 32 Page - Broadcom Corporation.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

데이터시트 다운로드

링크 URL