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TLE9255WLC 데이터시트(PDF) 92 Page - Infineon Technologies AG |
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TLE9255WLC 데이터시트(HTML) 92 Page - Infineon Technologies AG |
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92 / 100 page ![]() Data Sheet 92 Rev. 1.02 2018-02-02 TLE9255W Electrical Characteristics Figure 52 SPI timings MOSI hold time tMOSI_HO 50 – – ns – P_10.7.23 CSN “high” time tCSN_H 3.0 – – µs – P_10.7.24 Maximum signal rise time on SPI inputs: MOSI, SCLK and CSN tR_max –– 50 ns – P_10.7.25 Maximum signal fall time on SPI inputs: MOSI, SCLK and CSN tF_max –– 50 ns – P_10.7.26 MISO enable time tMISO_EN – – 120 ns – P_10.7.27 MISO enable time in Sleep Mode tMISO_EN_SLP –– 5.5 µs – P_10.7.36 MISO disable time tMISO_DIS –– 50 ns – P_10.7.28 MISO valid time tMISO_VAL – – 100 ns – P_10.7.29 CSN Timeout tCSN_TO 2.1 – 4 ms – P_10.7.30 1) Not subject to production test, specified by design. Table 22 SPI (cont’d) 4.75 V < VCC < 5.25 V; 3.0 V < VIO < 5.5 V; 5.5V < VBAT < 40V; RL =60 Ω; -40 °C < TJ < 150 °C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. CSN 70% VIO 30% VIO SCLK 70% VIO 30% VIO tbef tlead_NM or tlead_SL MOSI 70% VIO 30% VIO not defined MISO 70% VIO 30% VIO MSB (data out) tMISO_VAL MSB (data in) tMOSI_SU tMOSI_HO tSPI_CLK_H tSPI_CLK_L LSB (data out) LSB (data in) tCSN_H tlag tMISO_DIS Error tMISO_EN or tMISO_EN_SLP |
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