STV8216 datasheet(38/97 Pages) STMICROELECTRONICS

38 / 97 page

STV82x6

38/97

CTRL

Hardware Interface Control Register

Description

Provides all hardware controls to drive external components (SAW Filter, Audio Switches) and

additional Audio Decoder (Dolby Pro Logic) via register I2S including the Master and Quartz Clocks.

Bit Name

Reset

Function

Bit7

Reserved.

SCLPD_OFF

SCL Pulling-down System Disable

0: System is enabled

1: System is disabled

AUTO_OFF

Automatic Standard Recognition System Disable

0: System is enabled

1: System is disabled

Bits[4:3]

Reserved.

SOFT_LRESTART1

Softreset (active high) of Channel 1 detectors only.

SOFT_LRESTART2

Softreset (active high) of Channel 2 detectors only.

SOFTRST

General softreset (active high) to reset all hardware registers except for I²C data.

Address (hex): 03h

Type: R/W

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BUS_EXPAND[1:0]

I2S_EN

SDI_EN

MCK_EN

SYSCK_EN

Bit Name

Reset

Function

Bit 7

Reserved.

BUS_EXPAND[1:0]

Static control by I²C of hardware pins BUS1 and BUS0.

I2S_EN

When 1, the I²S hardware pin is enabled (SCK, WS, SDO)

SDI_EN

When 1, the SDI input pin is enabled (switch with ST output). Must be used when I²S mode is

selected.

Bit 2

Reserved.

MCK_EN

Master Clock Enable

Enables the master clock output (256.fs) to interface by I²S with the Dolby Pro Logic Decoder.

0: Disabled.

1: Enabled

SYSCK-EN

System Clock Enable

Enables the system clock output to provide the quartz clock required to interface with the Dolby Pro

Logic Decoder.

0: Disabled.

1: Enabled

STV8216 데이터시트(PDF) 38 Page - STMicroelectronics

STV8216 데이터시트(HTML) 38 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

데이터시트 다운로드

링크 URL