ISL9222

FN6643 Rev 1.00

Page 3 of 8

March 10, 2008

Pin Descriptions

VIN - Power input. The absolute maximum input voltage is

28V. A 1µF or larger value X5R ceramic capacitor is

recommended to be placed very close to the input pin for

decoupling purpose. Additional capacitance may be required

to provide a stable input voltage.

PPR - Open-drain power presence indication. The

open-drain MOSFET turns on when the input voltage is

above the POR threshold but below the OVP threshold and

off otherwise. This pin is capable to sink 10mA (minimum)

current to drive an LED. The maximum voltage rating for this

pin is 7V. This pin is independent on the EN-pin input.

JIGON - Output pin of the auxiliary 2-input OR gate. One of

the inputs is internal and is connected to the inverted PPR

logic. The other input is from the JIGIN pin driven externally

to provide system booting enable signal.

EN - Enable input. This is a logic input pin to disable or

enable the charger. Drive to HIGH to disable the charger.

When this pin is driven to LOW or left floating, the charger is

enabled. This pin has an internal 200k

 pull-down resistor.

GND - System ground.

JIGIN - One of the inputs of the 2-input auxiliary OR gate.

There is a 240k

 pull down resistor at this pin.

IREF - Charge-current program and monitoring pin. Connect

a resistor between this pin and the GND pin to set the

charge current limit determined by Equation 1:

the actual charge current during the entire charge cycle,

including the trickle, constant-current, and constant-voltage

phases. When disabled, VIREF = 0V.

BAT - Charger output pin. Connect this pin to the battery. A

1µF or larger X5R ceramic capacitor is recommended for

decoupling and stability purposes. When the EN pin is pulled

to logic HIGH, the BAT output is disabled.

EPAD - Exposed pad. Connect as much copper as possible

to this pad either on the component layer or other layers

through thermal vias to enhance the thermal performance.

LOGIC INPUT AND OUTPUTS

EN Pin Logic Input High

VIH

1.3

-

-

V

EN Pin Logic Input Low

VIL

--

0.5

V

EN Pin Internal Pull-Down Resistance

100

200

400

k



PPR Sink Current when LOW

Pin Voltage = 1V

10

20

-

mA

PPR Leakage Current When HIGH

-

-

1

µA

AUXILIARY OR GATE

Supply Voltage

2.5

-

5.0

V

JIGON High Level Output Voltage

VOH

VBAT -

0.1V

--

V

VBAT-

0.45V

--

V

JIGON Out Put Low Voltage

VOL

-

-

0.1

V

JIGIN Pin Logic Input High

VIH

VBAT = 2.5V

2.1

-

-

V

3.0V < VBAT < 5.0V

0.75 x

VBAT

--

V

JIGIN Pin Logic Input Low

VIL

VBAT = 2.5V

-

-

0.4

V

3.0V < VBAT < 5.0V

-

-

0.25x

VBAT

V

JIGIN Pin Internal Pull-Down Resistance

100

240

400

k



NOTES:

3. The output is used to test the VOS threshold. The output current will toggle between 0 and the CC current when VOS crosses over the threshold.

4. For junction temperature below +100°C.

5. The charge current can be affected by the thermal foldback function if the IC under the test setup cannot dissipate the heat.

Electrical Specifications

values are established under the recommended operating supply voltage range and ambient temperature

range, unless otherwise noted. (Continued)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

12089

-----------------

mA



=

(EQ. 1)