www.ti.com

DBB03

Baseband ASIC for Dolphin Chipset

SWRS027B – DECEMBER 2004 – REVISED MARCH 2005

DEVICE INFORMATION (continued)

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

P2.7/TA0

27

I/O

General-purpose digital I/O pin/Timer_A, compare: Out0 output

P3.0/STE0

28

I/O

General-purpose digital I/O pin/slave transmit enable - USART0/SPI mode

P3.1/SIMO0

29

I/O

General-purpose digital I/O pin/slave in/master out of USART0/SPI mode

P3.2/SOMI0

30

I/O

General-purpose digital I/O pin/slave out/master in of USART0/SPI mode

General-purpose digital I/O pin/external clock input - USART0/UART or SPI mode, clock

P3.3/UCLK0

31

I/O

output - USART0/SPI mode

P3.4/UTXD0

32

I/O

General-purpose digital I/O pin/transmit data out - USART0/UART mode

P3.5/URXD0

33

I/O

General-purpose digital I/O pin/receive data in - USART0/UART mode

P3.6

34

I/O

General-purpose digital I/O pin

P3.7

35

I/O

General-purpose digital I/O pin

P4.0/TB0

36

I/O

General-purpose digital I/O pin/Timer_B, capture: CCI0A/B input, compare: Out0 output

P4.1/TB1

37

I/O

General-purpose digital I/O pin/Timer_B, capture: CCI1A/B input, compare: Out1 output

P4.2/TB2

38

I/O

General-purpose digital I/O pin/Timer_B, capture: CCI2A/B input, compare: Out2 output

P4.3

39

I/O

General-purpose digital I/O pin

P4.4

40

I/O

General-purpose digital I/O pin

P4.5

41

I/O

General-purpose digital I/O pin

P4.6

42

I/O

General-purpose digital I/O pin

P4.7/TBCLK

43

I/O

General-purpose digital I/O pin/Timer_B, clock signal TBCLK input

P5.0

44

I/O

General-purpose digital I/O pin

P5.1

45

I/O

General-purpose digital I/O pin

P5.2

46

I/O

General-purpose digital I/O pin

P5.3

47

I/O

General-purpose digital I/O pin

P5.4/MCLK

48

I/O

General-purpose digital I/O pin/main system clock MCLK output

P5.5/SMCLK

49

I/O

General-purpose digital I/O pin/submain system clock SMCLK output

P5.6/ACLK

50

I/O

General-purpose digital I/O pin/auxiliary clock ACLK output

P5.7/TBOUT

General-purpose digital I/O pin/switch all PWM digital output ports to high impedance -

51

I/O

H

Timer_B7 TB0 to TB2

P6.0

59

I/O

General-purpose digital I/O pin

P6.1

60

I/O

General-purpose digital I/O pin

P6.2

61

I/O

General-purpose digital I/O pin

P6.3

2

I/O

General-purpose digital I/O pin

P6.4

3

I/O

General-purpose digital I/O pin

P6.5

4

I/O

General-purpose digital I/O pin

P6.6

5

I/O

General-purpose digital I/O pin

P6.7

6

I/O

General-purpose digital I/O pin

RST/NMI

58

I

Reset input, nonmaskable interrupt input port

TCK

57

I

Test clock. TCK is the clock input port for device programming test.

Test data input or test clock input. TDI is used as a data input port. The device protection

TDI/TCLK

55

I

fuse is connected to TDI.

TDO/TDI

54

I/O

Test data output port. TDO/TDI data output

TMS

56

I

Test mode select. TMS is used as an input port for device test.

NC

7, 10, 11

No internal connection

XIN

8

I

Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

XOUT

9

O

Output terminal of crystal oscillator XT1

XT2IN

53

I

Input port for crystal oscillator XT2. Only standard crystals can be connected.

XT2OUT

52

O

Output terminal of crystal oscillator XT2

5