80C86

FN2957 Rev 4.00

Page 24 of 38

August 19, 2015

(34)

TCLDX2

Data Hold Time

80C86 Outputs (In

Addition to 80C86 Self

Load)

10

10

ns

(35)

TCVNV

Control Active Delay (Note 11)

80C86 Outputs (In

Addition to 80C86 Self

Load)

5

45545

ns

(36)

TCVNX

Control Inactive Delay (Note 11)

10

45

10

45

ns

(37)

TAZRL

Address Float to Read Active

0

0

ns

(38)

TCLRL

RD Active Delay

10

165

10

100

ns

(39)

TCLRH

RD Inactive Delay

10

150

10

80

ns

(40)

TRHAV

RD Inactive to Next Address Active

TCLCL

- 45

TCLCL

- 40

ns

(41)

TCHDTL

Direction Control Active Delay

(Note 11)

50

50

ns

(42)

TCHDTH

Direction Control Inactive Delay

(Note 11)

30

30

ns

(43)

TCLGL

GT Active Delay

10

85

0

50

ns

(44)

TCLGH

GT Inactive Delay

10

85

0

50

ns

(45)

TRLRH

RD Width

2TCLCL

- 75

2TCLCL

- 50

ns

(46)

TOLOH

Output Rise Time

From 0.8V to 2.0V

20

15

ns

(47)

TOHOL

Output Fall Time

From 2.0V to 0.8V

20

15

ns

NOTES:

11. Signal at 82C84A or 82C88 shown for reference only.

12. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

13. Applies only to t2 state (8ns into t3).

14. The 80C86 actively pulls the RQ/GT pin to a logic one on the following clock low time.

15. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.

AC Electrical Specifications

tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are

not production tested. (Continued)

TIMING REQUIREMENTS

TEST CONDITIONS

80C86

80C86-2

UNITS

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX