Maxim Integrated │ 4

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Evaluates: MAX77752

MAX77752 Evaluation Kit

Table 1. Default Shunt Positions and Jumper Descriptions

Table 2. Default Voltages (CID4 = 0x07)

REGULATOR

EXPECTED VOLTAGE (V) (OPTION1)

BUCK1

1.8

BUCK2

1.35

BUCK3

1.05

LDO

1.8

LSW1

1.35

LSW2

OFF

REFERENCE

DESIGNATOR

DEFAULT

POSITION

FUNCTION

J1

OPEN

1-2: Connects LP_REQ to LP_MODE.

J2

OPEN

1-2: Connects VSYS to external regulators.

J3

OPEN

1-2: Connects VL to GPIO expander pullup resistors.

J4

2-3

1-2: Connects LP_MODE to VSYS.

2-3: Connects LP_MODE to GND.

J5

OPEN

1-2: Connects IN_PHUP to VSYS.

J6

OPEN

1-2: Connects VBUCK1 to Drain of LSW1 MOSFET.

J7

OPEN

1-2: Connects VBUCK2 to drain of LSW2 MOSFET.

J9

OPEN

1-2: Connects EREG_POK to GND.

J10

1-2

1-2: Connects VSYS to IN_LDO.

J101

2-3

1-2: Connects 3.3V to VL.

2-3: Connects 1.8V to VL.

J103

OPEN

1-2: Connects VIN to VUSB.

J200

1-2

1-2, 3-4: Connects the U200 amplifier to the gate of the Q200 load FET.

J208

1-2

1-2, 3-4: Connects the U204 amplifier to the gate of the Q204 load FET.

J209

1-2, 3-4

1-2, 3-4: Connects SYS to drain of the Q204 FET.

JU201

1-2, 3-4

1-2, 3-4: Connects VBUCK1 to drain of Q200 load FET.

JU202

1-2

1-2: Connects the U201 amplifier to the gate of the Q201 load FET.

JU203

1-2, 3-4

1-2, 3-4: Connects VBUCK2 to drain of Q201 load FET.

JU204

1-2

1-2: Connects the U202 amplifier to the gate of the Q202 load FET.

JU205

1-2, 3-4

1-2, 3-4: Connects VBUCK3 to drain of Q202 load FET.

JU206

1-2

1-2: Connects the U203 amplifier to the gate of the Q203 load FET.

JU207

1-2

1-2: Connects VLDO to drain of Q203 load FET.