K4S643233F-S(D)E/N/I/P

Rev. 1.5 Dec. 2002

CMOS SDRAM

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time

and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. Minimum tRDL=2CLK and tDAL(=tRDL + tRP) is required to complete both of last data wite command(tRDL) and precharge

command(tRP). tRDL=1CLK can be supported only in the case under 100MHz with manual precharge mode.

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

Parameter

Symbol

Version

Unit

Note

- 75

-1H

-1L

Row active to row active delay

15

19

19

ns

1

RAS to CAS delay

19

19

24

ns

1

Row precharge time

19

19

24

ns

1

Row active time

45

50

60

ns

1

100

us

Row cycle time

65

70

84

ns

1

Last data in to row precharge

2

CLK

2,3

Last data in to Active delay

tRDL + tRP

-

3

Last data in to new col. address delay

1

CLK

2

Last data in to burst stop

1

CLK

2

Col. address to col. address delay

1

CLK

4

Number of valid output data

CAS latency=3

2

ea

5

CAS latency=2

1

CAS latency=1

-

0

°C to 85°C for Extended, -40°C to 85°C for Industrial)

Parameter

Value

Unit

AC input levels (Vih/Vil)

2.4 / 0.4

V

Input timing measurement reference level

V

Input rise and fall time

tr/tf = 1/1

ns

Output timing measurement reference level

V

Output load condition

See Fig. 2

1200

Ω

870

Ω

Output

30pF

Vtt = 0.5 x VDDQ

50

Ω

Output

30pF

Z0 = 50

Ω

(Fig. 2) AC output load circuit

(Fig. 1) DC output load circuit