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TLS115D0 데이터시트(PDF) 8 Page - Infineon Technologies AG |
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TLS115D0 데이터시트(HTML) 8 Page - Infineon Technologies AG |
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8 / 26 page ![]() TLS115D0 High Precision Voltage Tracker General product characteristics Data Sheet 8 Rev. 1.00 2016-10-13 3.2 Functional range Note: Within the functional or operating range, the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the Electrical Characteristics table. 3.3 Thermal resistance Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org. Table 2 Functional range Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Input voltage range VIN 4 – 45 V – P_3.2.1 Adjust input voltage range (voltage tracking range) VADJ 2 – 14 V – P_3.2.2 Output capacitor COUT 1 ––µF –1)2) 1) The minimum output capacitance requirement is applicable for a worst case capacitance tolerance of 30%. 2) Not subject to production test, specified by design. P_3.2.3 Output capacitor’s Equivalent Series Resistance ESR (COUT) –– 5 Ω –2) P_3.2.4 Junction temperature Tj -40 – 150 °C –2) P_3.2.5 Table 3 Thermal resistance TLS115D0EJ in PG-DSO-8 EP package Parameter Symbol Values Unit Note or Test Condition Number Min. Typ. Max. Junction to case1) 1) Not subject to production test, specified by design. RthJC – 18 – K/W – P_3.3.1 Junction to pin1) RthJP – 85 – K/W – P_3.3.2 Junction to ambient1) RthJA –50 – K/W 2s2p board2) 2) Specified RthJA value is according to Jedec JESD51-2,-5,-7 at natural convection on FR4 2s2p board; The product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with 2 inner copper layers (2×70µm Cu, 2×35µm Cu). Where applicable a thermal via array under the exposed pad contacted the first inner copper layer. P_3.3.3 Junction to ambient1) RthJA – 157 – K/W 1s0p board, footprint only3) 3) Specified RthJA value is according to JEDEC JESD 51-3 at natural convection on FR4 1s0p board; The product (chip and package) was simulated on a 76.2×114.3×1.5 mm3 board with 1 copper layer (1 x 70 µm Cu). P_3.3.4 Junction to ambient1) RthJA – 77 – K/W 1s0p board, 300 mm2 heatsink area on PCB3) P_3.3.5 Junction to Ambient1) RthJA – 63 – K/W 1s0p board, 600 mm2 heatsink area on PCB3) P_3.3.6 |
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