9

ATSAM2133B

2694A–DRMSD–05/03

WA0 - 22

J2, K1, K2, K3, J4,

J3, K4, H5, G6, K5,

F6, J6, K6, G7, J7,

K7, K8, H8, K9, J9,

K10, J10, H10

OUT

External memory address (ROM/FLASH). Up to 16 Mega bytes.

WD0 - 15

F8, E7, F10, F9,

E8, E6, E9, E10,

D7, D9, C9, C10,

C8, B10, B9, A10

I/O

External ROM/FLASH data

WCS

G9

OUT

External ROM/FLASH chip select, active low.

WWE

G8

OUT

External FLASH write enable, active low.

WOE

H9

OUT

External ROM/FLASH output enable, active low.

LFT

A6

ANA

PLL low pass filter. Should be connected to an external RC network.

TEST

J1

IN

Test pin. Should be returned to GND.

PDWN

B8

IN

Power down, active low, all outputs except WCS, WWE, WOE are set to logic 0, the

PLL and crystal oscillator are stopped. If the power switch feature is used, then 2.5V

supply voltage is removed from the core. To exit from power down, PDWN must be set

to V

Table 3. Pin by Function - 100-ball LFBGA Package (Continued)

Pin Name

Pin Number

Type

Function