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ADL5336ACPZ-R7 데이터시트(PDF) 17 Page - Analog Devices

부품명 ADL5336ACPZ-R7
상세설명  Cascadable IF VGAs with Programmable RMS Detectors
PDF  30 Pages
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ADL5336ACPZ-R7 데이터시트(HTML) 17 Page - Analog Devices

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Data Sheet
ADL5336
Rev. C | Page 17 of 30
THEORY OF OPERATION
CIRCUIT DESCRIPTION
The ADL5336 contains two differential VGAs, each with a
programmable, internally connected, square law detector. VGA2
includes an input select switch that allows the user to choose
between two sets of differential inputs.
The signal path of each VGA, shown in Figure 59 and Figure 60,
consists of a variable input attenuator followed by a programmable
gain amplifier (PGA).
The input attenuator is built from an 18-section resistor ladder,
providing 1.34 dB of attenuation at each successive tap point.
The resistor ladder acts as a linear input attenuator, in addition
to providing an accurate 200 Ω input impedance. The variable
transconductance (gm) stages are used to select the attenuated
signal from the appropriate tap point along the ladder and feed
this signal to the fixed gain amplifier. To realize a continuous
gain control function from discrete tap points, the gain interpolator
creates a weighted sum of signals appearing on adjacent tap points
by carefully controlling the variable gm stages.
The weighted sum of the different tap points is fed into the
programmable gain stage. The programmable gain stage achieves
its different gain settings by changing the feedback network of
the amplifier.
The input attenuator and gm stages provide analog gain control
of 24 dB, whereas the programmable gain amplifier sets the
maximum gain of each VGA.
Table 4. VGA Gain Range
Maximum Gain Word
VGA1
VGA2
VGA1 Range (dB)
VGA2 Range (dB)
0
0
−14.5 to +9.5
−10 to +14
0
1
−12 to +12.0
−7.1 to +16.9
1
0
−10 to +14.0
−5 to +19
1
1
−8.4 to +15.6
−3.1 to +20.9
ATTENUATOR LADDER
200Ω
0dB
–1.4dB
–2.8dB
–23.8dB
OPP1
INP1
GAIN1
MODE
GAIN INTERPOLATOR
PGA
INM1
–22.4dB
gm STAGES
OPM1
PGA LINEAR
VOLTAGE GAIN:
G = 3, 4, 5, 6
Figure 59. VGA1 Functional Block Diagram
PGA LINEAR
VOLTAGE GAIN:
G = 5, 7, 9, 11
IP2A
IM2A
IP2B
IM2B
ATTENUATOR LADDER
200Ω
0dB
–1.4dB
–2.8dB
–23.8dB
OPP2
GAIN2
MODE
GAIN INTERPOLATOR
PGA
–22.4dB
gm STAGES
OPM2
Figure 60. VGA2 Functional Block Diagram



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