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M30102 데이터시트(PDF) 21 Page - Renesas Technology Corp |
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M30102 데이터시트(HTML) 21 Page - Renesas Technology Corp |
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21 / 164 page ![]() Under development Tentative Specifications REV.E1 Specifications in this manual are tentative and subject to change. Mitsubishi microcomputers M30100/M30102 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 20 Sub clock CM0i : Bit i at address 000616 CM1i : Bit i at address 000716 CM2i : Bit i at address 000C16 WDCi : Bit i at address 000F16 CM10 “1” Write signal WAIT instruction Main clock Interrupt request level judgment output RESET Software reset Details of divider CM04 fC32 XCIN 1/32 XCOUT Q S R XOUT CM05 fC XIN R Q S 1/2 1/2 1/2 1/2 CM06=0 CM17,CM16=00 CM06=0 CM17,CM16=01 CM06=0 CM17,CM16=10 CM06=1 CM06=0 CM17,CM16=11 d a b 1/2 c Main clock switching circuit Ring oscillator oscillation circuit CM20 Oscillation stop detection CM22 f1 fC CM07=0 fAD a d f8 f32 c b BCLK CM07=1 R CM02 1/2 fRING Divider fMAIN Microcomputer (Built-in feedback resistor) XCIN XCOUT Externally derived clock Open Vcc Vss Microcomputer (Built-in feedback resistor) XCIN XCOUT (Note) CCIN CCOUT RCd Note: Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. When the oscillation drive capacity is set to low, check that oscillation is stable. Clock Generating Circuit A ring oscillator is built into the microcomputer. The oscillation of the ring oscillator can be used as the BCLK by setting the main clock select bit (bit 2 of address 000C). Lower power consumption can be realized because the oscillating frequency of the ring oscillator is much lower compared to that of XIN. The frequency of the ring oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies and obtain the sufficient margin when designing application products. Clock Control Figure 1.8.3 shows the block diagram of the clock generating circuit. Figure 1.8.2. Examples of sub-clock Figure 1.8.3. Clock generating circuit |
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