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LTC1748

1748fa

14-Bit, 80Msps Low Noise ADC

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Sample Rate: 80Msps

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76.3dB SNR and 90dB SFDR (3.2V Range)

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72.6dB SNR and 90dB SFDR (2V Range)

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No Missing Codes

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Single 5V Supply

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Power Dissipation: 1.4W

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Selectable Input Ranges:

±1V or ±1.6V

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240MHz Full Power Bandwidth S/H

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Pin Compatible Family

25Msps: LTC1746 (14-Bit), LTC1745 (12-Bit)

50Msps: LTC1744 (14-Bit), LTC1743 (12-Bit)

65Msps: LTC1742 (14-Bit), LTC1741 (12-Bit)

80Msps: LTC1748 (14-Bit), LTC1747 (12-Bit)

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48-Pin TSSOP Package

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Telecommunications

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Receivers

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Cellular Base Stations

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Spectrum Analysis

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Imaging Systems

, LTC and LT are registered trademarks of Linear Technology Corporation.

The LTC

verter designed for digitizing high frequency, wide dy-

namic range signals. Pin selectable input ranges of

±1V

and

±1.6V along with a resistor programmable mode

allow the LTC1748’s input range to be optimized for a wide

variety of applications.

The LTC1748 is perfect for demanding communications

applications with AC performance that includes 76.3dB

SNR and 90dB spurious free dynamic range. Ultralow jitter

excellent noise performance. DC specs include

±3LSBINL

and no missing codes.

The digital interface is compatible with 5V, 3V, 2V and

LVDS logic systems. The ENC and ENC inputs may be

driven differentially from PECL, GTL and other low swing

logic families or from single-ended TTL or CMOS. The low

noise, high gain ENC and ENC inputs may also be driven

by a sinusoidal signal without degrading performance. A

separate output power supply can be operated from 0.5V

to 5V, making it easy to connect directly to any low voltage

DSPs or FIFOs.

The TSSOP package with a flow-through pinout simplifies

the board layout.

80Msps, 14-Bit ADC with a 2V Differential Input Range

14-BIT

PIPELINED ADC

14

S/H

AMP

±1V

DIFFERENTIAL

ANALOG INPUT

+

–

SENSE

4.7

µF

DIFF AMP

REFLA

REFHB

GND

1748 BD

ENC

4.7

µF

1

µF1µF

0.1

µF

0.1

µF

REFHA

REFLB

BUFFER

RANGE

SELECT

CORRECTION

LOGIC AND

SHIFT

REGISTER

OUTPUT

LATCHES

CONTROL LOGIC

OGND

0.5V

TO 5V

5V

0.1

µF

1

µF

1

µF

1

µF

D13

D0

CLKOUT

OF

•

•

•

ENC

DIFFERENTIAL

ENCODE INPUT

OE

MSBINV

0.1

µF

DESCRIPTIO

FEATURES

APPLICATIO S

BLOCK DIAGRA