Connection Diagrams

Dual-In-Line Package

TLC5596 – 10

Top View

Order Number MM82PC12J or N

See NS Package Number J24A or

N24A

Plastic Chip Carrier

TLC5596 – 12

Top View

Order Number MM82PC12V

See NS Package Number V28A

Logic Diagram

TLC5596 – 11

Logic Table A

STB

MD

Data Out

Equals

0

0

0

TRI-STATE

1

0

0

TRI-STATE

0

1

0

Data Latch

1

1

0

Data Latch

0

0

1

Data Latch

1

0

1

Data In

0

1

1

Data In

1

1

1

Data In

Note

CLR

K resets data latch to the output low state The data latch

clock is level sensitive a low level clock latches the data

Logic Table B

CLR

STB

Q

INT

0 RESET

0

0

0

1

10

0

0

1

10

K

10

1

1 RESET

0

0

0

10

0

0

1

Internal Service Request flip-flop

5