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SSM4567ACBZ-R7 데이터시트(PDF) 28 Page - Analog Devices

부품명 SSM4567ACBZ-R7
상세설명  Digital 2.5 W, 5.1 V, Boost Class-D Audio Amplifier with Output Sensing
PDF  52 Pages
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SSM4567ACBZ-R7 데이터시트(HTML) 28 Page - Analog Devices

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SSM4567
Data Sheet
Rev. 0| Page 28 of 52
TYPICAL APPLICATION CIRCUITS
SOFTWARE CONTROL MODE, I2S/TDM INTERFACE
Figure 54. Typical Application Circuit, I2S, Software Control Mode
Description
In this application circuit, the SSM4567 is controlled by an external master on the I2C interface. The I2C address is configured using the
LR_SEL/ADDR pin. The serial data interface is in PCM mode, as configured by the SEL pin.
Pin Configuration
Table 21. Pin Configuration for I2S Software Control Applications, Software Control Mode, I2S/TDM Interface
Hardware Pin
Connection
LR_SEL/ADDR
Connect to AGND for I2C Address 0x34; IOVDD for I2C Address 0x35; leave open for I2C Address 0x36.
SEL
Connect to IOVDD for PCM mode.
SNS_PDM_CLK/FSYNC
Connect to an external I2S/TDM frame sync clock signal.
DAC_PDM_CLK/BCLK
Connect to an external I2S/TDM bit clock signal.
SNS_PDM_DAT/SNS_SDATAO
Sends current, voltage, and battery sense data in I2S/TDM format to an external IC.
DAC_PDM_DAT/DAC_SDATAI
Receives a serial audio data signal in I2S/TDM format from an external IC.
SCL
Connect to the clock signal of an external I2C master IC.
SDA
Connect to data signal of an external I2C master IC.
I2S/TDM/
PDM
INTERFACE
H-BRIDGE
(5V)
V
SENSE
R
I
SENSE
Σ-Δ
CLASS-D
MOD
FILTERING
MODULATION
BOOST (5V)
OUTP
OUTN
22µF
10µF
1µF
2.2µH
VBAT
AGND
IOVDD
SSM4567
DAC_PDM_CLK/
BCLK
LR_SEL/
ADDR
SEL
BSTSW
IOVDD
BSTSW
VBST
VBST
PGND
SNS_PDM_CLK/
FSYNC
SNS_PDM_DAT/
SNS_SDATAO
DAC_PDM_DAT/
DAC_SDATAI
SCL
SDA
DAC
ADC
ADC
VBAT
0.1µF
IOVDD
1µF



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