6

TH7888A

1999A–IMAGE–09/03

Operating Conditions

Notes:

1. Ground: note that the package metal back is grounded.

2. In dynamic mode, to avoid possible damage to the device, the addition of a Schottky diode is recommended (for example;

diode reference BAR 43S) between VS1 and VSS ground in order to increase the potential on VS1, thus avoiding any direct

mode diode current during clock transitions.

Readout Mode

The serial readout register is operated in a two-phase transfer mode. However, there

are 6 separate command electrodes that should be connected differently, depending on

the required readout mode. The following table gives the connections to be made for

each mode.

Table 2. DC Characteristics

Parameter

Symbol

Value

Unit

Min

Typ

Max

Output amplifier drain supply

VDD1, VDD2

14.5

15

15.5

V

Protection drain bias

VDP

14.5

15

15.5

V

Reset bias

VDR

14.5

15

15.5

V

Antiblooming diode bias

VA

14.5

15

15.5

V

Register output gate bias

VGS

2.2

2.5

2.8

V

Output amplifier source supply

VS1(2), VS2

0

V

Ground(1)

VSS(2)

0V

Table 3. Readout Modes

Readout Modes

1 Output, VOS 1

1 Output, VOS2

(Mirror Effect)

2 Outputs (Parallel)

Drive Clocks (Signals)

ΦL1

Pins B2, B3, B1

Pins B2, A3, A1

Pins B2, B3, A1

ΦL2

Pins A2, A3, A1

Pins A2, B3, B1

Pins A2, A3, B1

Table 4. Timing Parameters

Definition

Symbol

Comments

Vertical transfer period

T

V

Nominal value = 800 nm

Vertical transfer subdivision

Tv = 8 x To

Rise time

tr

For vertical transfer clocks (between

10% and 90% of the transition time)

Fall time

tf

Readout register clock transition time

t1

Reset clock transition time

t2

Delay between output reset signal and reset clock

td