Triple PLL Field Programmable VCXO Clock

MDS 270 B

2

Revision 040705

Integrated Circuit Systems, Inc.

ICS270

PRELIMINARY INFORMATION

Pin Assignment

Pin Descriptions

13

4

12

5

11

VDD

8

9

10

GND

CLK3

CLK7

CLK1

CLK4

CLK8

17

16

CLK5

3

S1

VIN

S2

18

PDTS

1

X1

S0

VDD

20

X2

19

14

2

7

GND

CLK2

VDD

CLK6

15

6

20 pin (173 mil) TSSOP

Pin

Number

Pin

Name

Pin

Type

Pin Description

1VIN

Input

Voltage input to VCXO. Zero to 3.3 V signal which controls the VCXO

frequency

2

S0

Input

Select pin 0. Internal pull-up resistor.

3

S1

Input

Select pin 1. Internal pull-up resistor.

4VDD

Power

Connect to +3.3 V.

5

CLK1

Output

Output clock 1. Weak internal pull-down when tri-state.

6

CLK2

Output

Output clock 2. Weak internal pull-down when tri-state.

7

CLK3

Output

Output clock 3. Weak internal pull-down when tri-state.

8

CLK4

Output

Output clock 4. Weak internal pull-down when tri-state.

9

GND

Power

Connect to ground.

10

X1

XI

Crystal input. Connect this pin to a crystal.

11

X2

XO

Crystal Output. Connect this pin to a crystal.

12

VDD

Power

Connect to +3.3 V.

13

CLK5

Output

Output clock 5. Weak internal pull-down when tri-state.

14

CLK6

Output

Output clock 6. Weak internal pull-down when tri-state.

15

CLK7

Output

Output clock 7. Weak internal pull-down when tri-state.

16

CLK8

Output

Output clock 8. Weak internal pull-down when tri-state.

17

GND

Power

Connect to ground.

18

PDTS

Input

Power-down tri-state. Powers down entire chip and tri-states clock outputs

when low. Internal pull-up resistor.

19

VDD

Power

Connect to +3.3 V.

20

S2

Input

Select pin 2. Internal pull-up resistor.