ICS2309

MDS 2309 D

1

Revision 052405

Integrat ed Circuit Syst ems

Description

The ICS2309 is a low phase noise, high-speed PLL

based, low-skew zero delay buffer. Based on ICS’

proprietary low jitter Phase Locked Loop (PLL)

techniques, the device provides eight low skew outputs

at speeds up to 133 MHz at 3.3 V. The outputs can be

generated from the PLL (for zero delay), or directly

from the input (for testing), and can be set to tri-state

mode or to stop at a low level. The PLL feedback is

on-chip and is obtained from the CLKOUT pad.

The ICS2309 is available in two different versions. The

ICS2309-1 is the base part. The ICS2309-1H is a high

drive version with faster rise and fall times.

Features

capability at TTL levels

only)

(16-pin TSSOP only)

Block Diagram

CLKA4

CLKB1

CLKA3

CLKB2

CLKB3

CLKA2

CLKA1

CLKB4

CLKIN

Control

Logic

1

0

S2, S1 2

PLL

VDD

2

GND

2

CLKOUT