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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LPC81xM 데이터시트(PDF) 39 Page - NXP Semiconductors |
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LPC81xM 데이터시트(HTML) 39 Page - NXP Semiconductors |
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39 / 78 page  LPC81XM All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 4.6 — 4 April 2018 39 of 78 NXP Semiconductors LPC81xM 32-bit ARM Cortex-M0+ microcontroller Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; low-current mode. 1 MHz - 6 MHz: IRC enabled; PLL disabled. 12 MHz: IRC enabled; PLL disabled. 24 MHz: IRC enabled; PLL enabled. 30 MHz: IRC disabled; SYSOSC enabled; PLL enabled. Fig 16. Sleep mode: Typical supply current IDD versus temperature for different system clock frequencies Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register (PDSLEEPCFG = 0x0000 18FF). Fig 17. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD |
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