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ICS8516 데이터시트(PDF) 6 Page - Integrated Device Technology

부품명 ICS8516
상세설명  Low Skew, 1-to-16 Differential-to-LVDS Clock Distribution Chip
PDF  16 Pages
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS8516 데이터시트(HTML) 6 Page - Integrated Device Technology

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LOW SKEW, 1-TO-16
DIFFERENTIAL-TO-LVDS CLOCK DISTRIBUTION CHIP
8516 DATA SHEET
6
REVISION B 6/11/15
ADDITIVE PHASE JITTER
Additive Phase Jitter @ 155.52MHz
(12kHz to 20MHz)
= 148fs typical
-50
-60
-70
-80
-90
-100
-100
-120
-130
-140
-150
-160
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of the
noise power present in a 1Hz band at a specified offset from the
fundamental frequency to the power value of the fundamental.
This ratio is expressed in decibels (dBm) or a ratio of the power in
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher
than the noise floor of the device. This is illustrated above. The
the 1Hz band to the power in the fundamental.When the required
offset is specified, the phase noise is called a dBc value, which
simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
device meets the noise floor of what is shown, but can actually
be lower. The phase noise is dependant on the input source and
measurement equipment.
OFFSET FROM CARRIER FREQUENCY (HZ)



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