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WM8988 데이터시트(PDF) 13 Page - Cirrus Logic

부품명 WM8988
상세설명  Stereo CODEC for Portable Audio Applications
PDF  58 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8988 데이터시트(HTML) 13 Page - Cirrus Logic

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WM8988
Rev 4.2
13
AUDIO INTERFACE TIMING – SLAVE MODE
Figure 3 Digital Audio Data Timing
– Slave Mode
Test Conditions
DCVDD = 1.42V, DBVDD = 3.3V, DGND = 0V, TA = +25
oC,
Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
tBCH
20
ns
BCLK pulse width low
tBCL
20
ns
DACLRC set-up time to BCLK rising edge
tLRSU
10
ns
DACLRC hold time from BCLK rising edge
tLRH
10
ns
DACDAT hold time from BCLK rising edge
tDH
10
ns
ADCDAT propagation delay from BCLK falling edge
tDD
10
ns
Note:
BCLK period should always be greater than or equal to MCLK period.
BCLK
LRC
t
BCH
t
BCL
t
BCY
DACDAT
ADCDAT
t
LRSU
t
DS
t
LRH
t
DH
t
DD



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