AD9508BCPZ datasheet(39/40 Pages) AD

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Data Sheet

AD9508

Rev. G | Page 39 of 40

Table 34. Output Driver, Power Down, and Sync

Address

Bits

Bit Name

Description

0x2B

PD_3

Divider 3 power-down

SYNCMASK3

Setting this bit masks OUT3 from the output sync function

0 = Divider 3 is synchronized during output sync (default)

1 = Divider 3 is excluded from an output sync

[5:4]

OUT3 Driver Phase[1:0]

These bits determine the phase of the OUT3 driver

00 = force high

01 = noninverting

10 = inverting

11 = force low

[3:1]

OUT3 Mode[2:0]

These bits determine the OUT3 driver mode

000 = LVDS 0.5 × 3.5 mA (1/2 amplitude)

001 = LVDS 0.75 × 3.5 mA (3/4 amplitude)

010 = LVDS 1 × 3.5 mA (default)

011 = LVDS 1.25 × 3.5 mA (1.25 amplitude)

100 = HSTL 1 × 8 mA (normal amplitude)

101 = HSTL boost mode (LVPECL compatible, 40% additional amplitude), approximately

11 mA.

110 = high-Z/CMOS

111 = high-Z/CMOS

Reserved

0b = default

0x2C

EN_CMOS_3P

Setting this bit enables the OUT3P CMOS driver

0 = disables the OUT3P CMOS driver (default)

1 = enables OUT3P CMOS driver

[6:5]

CMOS_3P_PHASE[1:0]

These bits determine the phase of the OUT3P CMOS driver

00 = force high (default)

01 = noninverting

10 = inverting

11 = force low

EN_CMOS_3N

Setting this bit enables the OUT3N CMOS driver

0 = disables the OUT3N CMOS driver (default)

1 = enables OUT3N CMOS driver

[3:2]

CMOS_3N_PHASE[1:0]

These bits determine the phase of the OUT3N CMOS driver

00 = force high (default)

01 = noninverting

10 = inverting

11 = force low

[1:0]

Reserved

00b = default

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