LTC6953 datasheet(37/56 Pages) AD

37 / 56 page

LTC6953

Rev 0

For more information www.analog.com

Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

JESD204B DESIGN EXAMPLE USING EZSync MULTICHIP

This design example consists of a system of four

JESD204B analog-to-digital converters (ADCs), four

JESD204B digital-to-analog converters (DACs), and a

JESD204B compatible FPGA. All of the data convert-

ers (ADCs and DACs) and the FPGA require JESD204B

subclass 1 device clocks and SYSREFs, and the FPGA

requires an extra management clock. Additionally, the

ADCs require a low noise clock of less than 100fs total

RMS jitter. This leads to a total of 19 separate signals to

generate, with frequencies listed below. For this exam-

ple, the SYSREF frequencies for all devices are the same

and should output four pulses upon a SYSREF request

rising edge:

fADC–CLK = 500MHz

fDAC–CLK = 4000MHz

fFPGA–CLK = 125MHz

fFPGA–MGMT = 100MHz

fSYSREF = 12.5MHz

To determine which multichip configuration to use, we

utilize the flowchart in Figure 10. This example has nine

total JESD204B device clock/SYSREF pairs, four of which

need to be less than 100fs total jitter. We also need one

additional non-low noise standalone clock for the FPGA.

Therefore:

TP = 9

LNP = 4

TS = 1

LNS = 0

Based on these inputs, Figure 10 suggests using the

EZSync multichip protocol with request pass-through

topology shown in Figure 7, using one CONTROLLER and

one FOLLOWER chip. Noting that the use of LTC6953

for any FOLLOWER chips is recommended, Figure 26

Figure 26. Block Diagram for JESD204B EZSync Multichip Design Example

SYNC AND

SYSREF CTRL

M10

SSRQ BIT

SYNC AND

SYSREF CTRL

M10

SSRQ BIT

EZS_SRQ±

ADC0

SYSREF

CLK

ADC1

SYSREF

CLK

SYSREF

CLK

ADC2

ADC3

DEV CLK

SYSREF

MGMT CLK

FPGA

SYSREF

CLK

DAC3

SYSREF

CLK

DAC2

DAC1

DAC0

LTC6953

CONTROLLER

LTC6953

FOLLOWER

IN±

EZS_SRQ±

INPUT/OUTPUT TERMINATIONS AND

AC COUPLING CAPS NOT SHOWN.

6953 F26

IN±

CLOCK

GENERATOR

LTC6953 데이터시트(PDF) 37 Page - Analog Devices

LTC6953 데이터시트(HTML) 37 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

데이터시트 다운로드

링크 URL