SM6800A

NIPPON PRECISION CIRCUITS INC.—2

BLOCK DIAGRAM

PIN DESCRIPTION

Number

2. Ip

= input pin with built-in pull-up resistor

Function

1

VDD1

–

Supply (input system)

2

IN

I

Signal input

3

EQP

I

Equalizer network connection

4

EQN

I

Equalizer network connection

5

VSS1

–

Ground (input system)

6

VREF3

–

Reference voltage 3 (internal bias voltage monitor. No connection for normal operation)

7

VREF2

–

Reference voltage 2 (internal bias voltage monitor. No connection for normal operation)

8

VREF1

–

Reference voltage 1 (bias voltage)

9

PDWN

I

Power-down control (active LOW)

10

MUTEN

I

Mute control (active LOW)

11

VDD2

–

Supply (OUTN stage)

12

OUTN

O

Speaker minus (–) output

13

VSS2

–

Ground (OUTP and OUTN stages)

14

OUTP

O

Speaker plus (

+) output

15

VDD3

–

Supply (OUTP stage)

16

VSS3

–

Ground (output system)

17

TM1

I

Dynamic range compression mode setting 1

18

TM2

I

Dynamic range compression mode setting 2

19

TEST

Ip

Test pin (HIGH: normal operation, LOW: test mode)

20

PROT

O

Protection circuit output (HIGH: protection circuit operation, LOW: normal operation)

IN

VSS2

PDWN

VDD2

VREF1

OUTN

MUTEN

VREF3

VREF2

PWM

Modulator

OSC

VDD3

VSS3

EQP

VSS1

VDD1

EQN

+

−

VREF1 VREF2

TEST

TM2

TM1

+

−

VREF1 VREF2

VREF3

MUTE,

POWERDOWN,

PROTECTION

LEVEL

SHIFTER

OUTP

BIAS, VREF1,

VREF2, VREF3

BUFFER

BUFFER

LEVEL

SHIFTER