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AD9530BCPZ 데이터시트(PDF) 4 Page - Analog Devices

부품명 AD9530BCPZ
상세설명  4 CML Output, Low Jitter Clock Generator
PDF  41 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9530BCPZ 데이터시트(HTML) 4 Page - Analog Devices

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AD9530
Data Sheet
Rev. 0 | Page 4 of 41
SPECIFICATIONS
Typical values are given for VDD = 2.5 V ± 5%, TA = 25°C, unless otherwise noted. Minimum and maximum values are given over the full VDD
range and TA (−40°C to +85°C) variations listed in Table 1.
SUPPLY VOLTAGE AND TEMPERATURE RANGE SPECIFICATIONS
Table 1.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY VOLTAGE
VDD
2.375
2.5
2.625
V
2.5 V ± 5%
TEMPERATURE
Ambient Temperature Range
TA
−40
+25
+85
°C
Junction Temperature1
TJ
115
°C
1 The is the maximum junction temperature for which device performance is guaranteed. Note that the Absolute Maximum Ratings section may have a higher
maximum junction temperature, but device operation or performance is not guaranteed above the number that appears here. To calculate the junction temperature,
see the Power Dissipation and Thermal Considerations section.
SUPPLY CURRENT SPECIFICATIONS
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SUPPLY CURRENT OTHER THAN CLOCK THE
DISTRIBUTION CHANNEL
Current listed in the Typ column is at nominal VDD at
25°C; current listed in the Max column is at
maximum VDD and worst case temperature
Typical Operation 1
fRTWO = 5300.16 MHz; VCO mode = low power;
REFA enabled at 110.42 MHz; REFB disabled;
R divider = 1; M1 and M3 divider = 3; M2 divider =
powered down; phase frequency detector (PFD) =
110.42 MHz; OUT1 CML output at 1766.72 MHz;
OUT2, OUT3, and OUT4 outputs and dividers
powered down; single-ended output swing level =
800 mV; outputs terminated externally with 50 Ω
to VDD
Reference Input VDD (Pin 3 and Pin 7)
8.2
10.7
mA
Combined current of Pin 3 and Pin 7
PLL VDD (Pin 12)
18.2
24
mA
Rotary Travelling Wave Oscillator (RTWO) VDD
(Pin 20 to Pin 23)
747
860
mA
Combined current of Pin 20 to Pin 23
SUPPLY CURRENT FOR AN INDIVIDUAL CLOCK
DISTRIBUTION CHANNEL
Each output channel has a dedicated VDD pin; all
current values are listed for a single driver supply
pin operating at 1766.72 MHz; output terminated
externally, 50 Ω to VDD; these specifications include
the current required for the external load resistors
CML
Internal Termination Disabled
800 mV
28.8
35.5
mA
900 mV
30.7
37.6
mA
1000 mV
32.6
39.8
mA
1100 mV
34.5
41.8
mA
Internal Termination Enabled
800 mV
47.6
57.2
mA
900 mV
51.5
61.5
mA
1000 mV
55.3
65.8
mA
1100 mV
59.0
70.1
mA



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