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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AD9545 데이터시트(PDF) 19 Page - Analog Devices |
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AD9545 데이터시트(HTML) 19 Page - Analog Devices |
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19 / 157 page  Data Sheet AD9545 Rev. A | Page 19 of 157 Parameter Min Typ Max Unit Test Conditions/Comments Low Period of the SCL Clock, tLOW 1.3 µs High Period of the SCL Clock, tHIGH 0.6 µs SCL/SDA Rise Time, tR 20 + 0.1 × CB 300 ns SCL/SDA Fall Time, tF 20 + 0.1 × CB 300 ns Data Setup Time, tSU; DAT 100 ns Data Hold Time, tHD; DAT 100 ns Capacitive Load for Each Bus Line, CB 400 pF LOGIC INPUT SPECIFICATIONS (RESETB, M0 TO M6) Table 20. Parameter Min Typ Max Unit Test Conditions/Comments RESETB Valid for 3.3 V ≥ VDDIOA ≥ 1.8 V; internal 100 kΩ pull-up resistor Input Voltage High, VIH VDDIOA − 0.4 V Low, VIL 0.4 V Input Current High, IINH 1 µA Low, IINL ±15 ±125 µA LOGIC INPUTS (M0 to M6) Valid for 3.3 V ≥ VDDIOx ≥ 1.8 V; VDDIOA applies to the M5 pin and the M6 pin; VDDIOB applies to the M0, M1, M2, M3, and M4 pins; the M3 and M4 pins have internal 100 kΩ pull-down resistors Frequency Range 51 MHz Input Voltage High, VIH VDDIOx − 0.4 V Low, VIL 0.4 V Input Current, IINH, IINL ±15 ±125 µA |
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