AD9545BCPZ datasheet(58/157 Pages) AD

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AD9545BCPZ 데이터시트(PDF) 58 Page - Analog Devices

부품명	AD9545BCPZ

상세설명	Quad Input, 10-Output, Dual DPLL/IEEE 1588 1 pps Synchronizer and Jitter Cleaner

PDF	157 Pages

Scroll/Zoom	100%

제조업체	AD [Analog Devices]

홈페이지	http://www.analog.com

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58 / 157 page

AD9545

Data Sheet

Rev. A | Page 58 of 157

For example, determine the value of the Qxy phase bit field

necessary to yield a 14% pulse width given E = 7301. Solving

Equation 1 for Qxy phase yields the following:

Qxy Phase = Pulse Width × E/100

= 14 × 7301/100

= 1022 (nearest integer)

= 0x0000003FE (hexadecimal)

The user has the option to adjust the output pulse width only

prior to execution of the first subsequent phase offset. After

invoking a subsequent phase offset, pulse width control is no

longer available. To change the output pulse width after

executing the first subsequent phase offset, the user must issue a

Q divider sync (see the Distribution Output Clock Synchronization

section), at which point the Q divider is ready to accept a new

initial phase offset, a new output pulse width ,and subsequent

phase offsets.

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