LTC6952 datasheet(42/80 Pages) AD

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LTC6952

6952f

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Preliminary Technical Data

Advance Product Information Subject to Change

Rev PrA

APPLICATIONS INFORMATION

Figure 28. Block Diagram for JESD204B EZSync Standalone Design Example

Reference and VCO Assumptions

For this example, assume the available reference is a

100MHz sine wave oscillator with 8dBm output power, and

the VCO is a 4000MHz oscillator with a KVCO of 5MHz/V,

output power of 7dBm, and phase noise of –115dBc/Hz

at 10kHz.

fREF = 100MHz

fVCO = 4000MHz

KVCO = 5MHz/V

Design Procedure

Designing and enabling this clock generation solution

consists of the following steps:

1. Determine R and N divider values

2. Determine the optimum loop bandwidth

3. Select loop filter component values

4. Determine all output modes

5. Determine all M divider values

6. Determine all digital delay values

7. Program the IC with the correct divider values,

output delays, and other settings

8. Synchronize the outputs

9. Place the SYSREF outputs in a lower power mode

until the next SYSREF request (optional, see Opera-

tions section)

10. Place IC into SYSREF request mode (SRQMD=1) and

send a SYSREF request when needed

11. Return IC into SYNC mode (SRQMD=0) and place the

SYSREF outputs into a lower power mode for power

savings (optional).

Note that synchronization MUST be performed before a

SYSREF request. The synchronization must be repeated

only if the divider setting is changed, or if the divider is

powered down.

Determining R and N Divider Values

Following the “Loop Filter Design” algorithm, first deter-

mine all the divider values. From the Electrical Character-

istics, the maximum fPFD is 167MHz, which is larger than

the fREF of 100MHz. Therefore R should be “1” noting

that maximizing fPFD in a data converter application will

minimize integrated jitter. Use Equation 4 to determine

fPFD and Equation 6 to determine N:

R = 1

fPFD = fREF/R = 100MHz

N = fVCO/fPFD = 40

NDIV

VCO

RDIV

LF(s)

EZS_SRQ±

SYNC AND

SYSREF CTRL

M10

REF

SSRQ BIT

ADC0

SYSREF

CLK

ADC1

SYSREF

CLK

DEV CLK

SYSREF

MGMT CLK

FPGA

SYSREF

CLK

DAC1

DAC0

LTC6952

VCO±

INPUT/OUTPUT TERMINATIONS AND

AC COUPLING CAPS NOT SHOWN.

6952 F28

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