AD9510_16 datasheet(48/56 Pages) AD

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AD9510

Data Sheet

Rev. C | Page 48 of 56

Reg.

Addr.

(Hex) Bit(s) Name

Description

[4:2] Prescaler value

(P/P + 1)

[4]

[3]

[2]

Mode

Prescaler Mode

Divide by 1

Divide by 2

2/3

4/5

8/9

16/17

32/33

Divide by 3

DM = dual modulus, FD = fixed divide.

[5]

Not used.

[6]

B counter bypass

Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is

divided by 1. This allows the prescaler setting to determine the divide for the N divider.

[7]

Not used.

[5:0] 14-bit reference

counter, R MSBs

R divider MSB[13:8].

[7:0] 14-bit reference

counter, R LSBs

R divider MSB[7:0].

[1:0] Antibacklash pulse

width

[1]

[0]

Antibacklash Pulse Width (ns)

1.3 (default)

2.9

6.0

1.3

[4:2]

Not used

[5]

Digital lock detect

window

[5]

Digital Lock Detect Window (ns)

Digital Lock Detect Loss of Lock Threshold (ns)

0 (default)

9.5

3.5

If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window

time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the

loss of lock threshold.

[6]

Lock detect disable 0 = normal lock detect operation (default), 1 = disable lock detect.

[7]

Not used.

Unused

0E33

Not used.

Fine delay adjust

[0]

Delay control

Delay block control bit.

OUT5

Bypasses delay block and powers it down (default = 1b).

OUT6

[7:1]

Not used.

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