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ADM3085 데이터시트(PDF) 6 Page - Analog Devices

부품명 ADM3085
상세설명  High-Speed (10Mbps), Fail-Safe, RS-485/RS-422 Transceivers with Slew-Rate-Limiting and 5kV ESD Protection
PDF  14 Pages
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ADM3085 데이터시트(HTML) 6 Page - Analog Devices

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ADM3082/ADM3085/ADM3088
–6 –
PRELIMINARY TECHNICAL DATA
ADM3082/ADM3085/ADM3088 SPECIFICATIONS (continued)
SWITCHING CHARACTERISTICS—ADM3088
(VCC = +5V ±5%, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V and TA = +25°C.) (Note 1)
Parameter
Min
Typ
Max
Units
Test Conditions/Comments
Driver Input-to-Output, tDPLH
34
60
ns
Figures 2 and 5, RDIFF = 54 ,
Driver Input-to-Output, tDPHL
34
60
ns
CL1 = CL2 = 100pF
Driver Output Skew,|tDPLH -tDPHL|, tDSKEW
–2.5
±10
ns
Figures 2 and 5, RDIFF = 54 ,
CL1 = CL2 = 100pF
Driver Rise or Fall Time, tDR, tDF
14
25
ns
Figures 7 and 9, RDIFF = 54 ,
CL1 = CL2 = 100pF
Maximum Data Rate, fMAX
10
Mbps
Driver Enable to Output High, tDZH
150
ns
Figures 5 and 6, CL = 100pF,
S2 closed
Driver Enable to Output Low, tDZL
150
ns
Figures 5 and 6, CL = 100pF,
S1 closed
Driver Disable Time from Low, tDLZ
100
ns
Figures 5 and 6, CL = l5pF,
S1 closed
Driver Disable Time from High, tDHZ
100
ns
Figures 5 and 6, CL = l5pF,
S2 closed
Receiver Input-to-Output, tRPLH, tRPHL
106
150
ns
Figure 7; |VID|
2.0V;
rise and fall time of VID
l5ns
DifferentialReceiver Skew, tRSKD
0
±10
ns
Figures 7; |VID|
2.0V;
|tRPLH – tRPHL|
rise and fall time of VID
l5ns
Receiver Enable to Output Low, tRZL
20
50
ns
Figures 7 and 8, CL = 100pF,
S1 closed
Receiver Enable to Output High, tRZH
20
50
ns
Figures 7 and 8, CL = 100pF,
S2 closed
Receiver Disable Time from Low, tRLZ
20
50
ns
Figures 7 and 8, CL = 100pF,
S1 closed
Receiver Disable Time from High, tRHZ
20
50
ns
Figures 7 and 8, CL = 100pF,
S2 closed
Time to Shutdown, tSHDN
50
200
600
ns
(Note 5)
Driver Enable from Shutdown
250
ns
Figures 5 and 6, CL = l5pF,
toOutput High, tDZH(SHDN)
S2 closed
Driver Enable from Shutdown
250
ns
Figures 5 and 6, CL = l5pF,
to Output Low, tDZL(SHDN)
S1 closed
Receiver Enable from Shutdown
3500
ns
Figures 7 and 8, CL = 100pF,
to Output High, tRZH(SHDN)
S2 closed
Receiver Enable from Shutdown
3500
ns
Figures 7 and 8, CL = 100pF,
to Output Low, tRZL(SHDN)
S1 closed
NOTES
5The device is put into shutdown by bringing
RE high and DE low. If the enable inputs are in this state for less than 50ns, the device is guaranteed not to enter shut-
down. If the enable inputs are in this state for at least 600ns, the device is guaranteed to have entered shutdown.
REV. PrA 02/02



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