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CM6503IP 데이터시트(PDF) 8 Page - List of Unclassifed Manufacturers

부품명 CM6503IP
상세설명  8-PIN SINGLE PFC CONTROLLER WITH 50% PWM CLOCK SIGNAL
PDF  13 Pages
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CM6503/4
8-PIN SINGLE PFC CONTROLLER WITH 50% PWM CLOCK SIGNAL
2002/07/16
Preliminary Rev. 0.2
Champion Microelectronic Corporation
Page 8
For steady state and for the each phase angle, boost
converter DC equation at continuous conduction mode is:
)
1
(
1
d
V
V
in
out
−
=
(4)
Rearrange above equations, (1), (2),(3), and (4) in term of
Vout and d, boost converter duty cycle and we can get
average boost diode current equation (5):
e
out
d
R
V
d
I
×
−
=
2
)
1
(
(5)
Also, the average diode current can be expressed as:
dt
t
I
T
I
off
T
d
sw
d
⋅
=
∫
)
(
1
0
(6)
If the value of the boost inductor is large enough, we can
assume
d
d
I
t
I
~
)
(
. It means during each cycle or we
can say during the sampling, the diode current is a
constant.
Therefore, equation (6) becomes:
)
1
(
'
d
I
d
I
T
t
I
I
d
d
sw
off
d
d
−
×
=
×
=
×
=
(7)
Combine equation (7) and equation (5), and we get:
sw
off
e
out
d
e
out
d
e
out
d
T
t
R
V
I
R
V
d
I
R
V
d
d
I
×
=
∴
×
=
∴
×
=
×
'
2
'
'
)
(
(8)
From this simple equation (8), we implement the PFC control
section of the CM6503.
Leading/Trailing Modulation
Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will turn
ON right after the trailing edge of the system clock. The error
amplifier output is then compared with the modulating ramp.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned OFF. When
the switch is ON, the inductor current will ramp up. The
effective duty cycle of the trailing edge modulation is
determined during the ON time of the switch. Figure 2 shows
a typical trailing edge control scheme.
In case of leading edge modulation, the switch is turned OFF
right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during OFF time of the switch. Figure 3 shows a leading
edge control scheme.



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