HTOP01

www.honeywell.com

2

FUNCTIONAL BLOCK DIAGRAM

SIGNAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS (1)

Symbol

Parameter

Rating

Units

Min

Max

VDD

Supply Voltage (2)

-0.5

6.5

Volts

VPIN

Voltage on Any Pin (2)

-0.5

VDD+0.5

Volts

TSTORE

Storage Temperature

-65

300

°C

IOUT

Average Output Current

50

mA

ESD

Electrostatic Discharge Protection Voltage (3)

1000

V

PJC

Package Thermal Resistance

(Junction-to-Case)

14 Pin DIP

15.0

°C/W

(1)

Stresses in excess of those listed above may result in immediate permanent damage to the device. These are stress ratings only, and

operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability.

(2)

Voltage referenced to VSS.

(3)

Class 2 Electrostatic Discharge (ESD) input protection voltage per MIL-STD-883, Method 3015

Pin Name

Pin

Number

Description

SEL

13

Digital input pin. Selects either internal clock (SEL=0) or externally applied clock

(SEL=1).

XCLK

2

Digital input pin. External clock input. When SEL=1, XCLK is enabled, and the

internal ping-pong amplifier action occurs on each XCLK edge. When SEL=0, XCLK

is disabled. When not used, XCLK should be connected to VDD or VSS.

SHDN

7

Digital input pin. Power Shutdown control input. When SHDN=1, all analog circuitry is

de-powered/disabled, and only leakage current will flow into VDD. When SHDN=0,

normal circuit operation occurs.

INPA, INPB

4, 11

Non-

inverting amplifier inputs for amplifier “A” and “B” respectively.

INMA, INMB

5,10

Inverting amplifier inputs

for amplifier “A” and “B” respectively.

OUTA, OUTB

1, 14

Amplifier “A” and “B” outputs.

VDD

3, 9

Positive supply connection.

VSS

6,12

Negative supply connection.

No connect

8

Pin not used.

14

13

12

11

1

2

3

4

VDD

INPA

INMA

VSS

SEL

VSS

OUTB

INPB

5

6

7

SHDN

OUTA

XCLK

9

8

INMB

VDD

No

connection

10

HTOP01

14 Pin DIP

OUT

INP

INM

1

2

1

2

Open

Closed

t

1, 2

-

+

+

-

2

1

2

1

A2

2

-

+

+

-

1

2

1

2

A1

1

Output

Stage