© 2005 Fairchild Semiconductor Corporation

DS500040

www.fairchildsemi.com

August 1997

Revised June 2005

74VCX162244

Low Voltage 16-Bit Buffer/Line Driver

with 3.6V Tolerant Inputs and Outputs

and 26: Series Resistor in Outputs

General Description

The VCX162244 contains sixteen non-inverting buffers

with 3-STATE outputs to be employed as a memory and

address driver, clock driver, or bus oriented transmitter/

receiver. The device is nibble (4-bit) controlled. Each nibble

has separate 3-STATE control inputs which can be shorted

together for full 16-bit operation.

The 74VCX162244 is designed for low voltage (1.2V to

74VCX162244 is also designed with 26

: series resistors in

the outputs. This design reduces line noise in applications

such as memory address drivers, clock drivers, and bus

transceivers/transmitters.

The 74VCX162244 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

■ 3.6V tolerant inputs and outputs

■ 26

: series resistors in outputs

■ Power-off high impedance inputs and outputs

■ Supports live insertion and withdrawal

■ Latch-up performance exceeds 300 mA

■ ESD performance:

Human body model

! 2000V

Machine model

! 200V

■ Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA)

Note 1: To ensure the high-impedance state during power up or power

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Note 2: Ordering Code “G” indicates Trays.

Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

Package Number

Package Description

74VCX162244G

(Note 2)(Note 3)

BGA54A

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

74VCX162244MTD

(Note 3)

MTD48

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

■ Uses proprietary noise/EMI reduction circuitry