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IDT5V927 데이터시트(PDF) 2 Page - Integrated Device Technology

부품명 IDT5V927
상세설명  Quad Output Clock Generator
PDF  6 Pages
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT5V927 데이터시트(HTML) 2 Page - Integrated Device Technology

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INDUSTRIALTEMPERATURERANGE
IDT5V927
QUADOUTPUTCLOCKGENERATOR
REF
X1
X2
VDD
Q0
GND
Q1
VDDQ
1
2
3
4
5
6
7
8
S0
S1
OE
GND
Q3
GND
Q2
VDDQ
9
10
11
12
13
14
15
16
PIN CONFIGURATION
TSSOP
TOP VIEW
CRYSTAL SPECIFICATION
The crystal oscillators should be fundamental mode quartz crystals:
overtone crystals are not suitable. Crystal frequency should be specified
for parallel resonance with 50
Ω maximum equivalent series resonance.
CrystaltuningcapacitorsshouldbeconnectedfromX2/REFtoGNDandfrom
X1 to GND.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max.
Unit
VDD/VDDQ
SupplyVoltagetoGround
– 0.5 to +4.6
V
VI
InputVoltage
– 0.5 to +4.6
V
IO
OutputCurrent
±50
mA
TSTG
StorageTemperature
– 65 to +150
°C
TJ
JunctionTemperature
150
°C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
PIN DESCRIPTION
Pin Name Type
Description
S[1:0]
I
Three level divider/mode select pins. Float to MID.
OE
I
Outputenablebar. OE hasapull-down. OutputQ[1:3]tristated
when HIGH. Output Q0 remains running when in PLL mode
andtri-stateswheninTESTmode.
X1
I
Crystaloscillatorinput.ConnecttoGNDifoscillatornotrequired.
X2
I
Crystaloscillatoroutput. Leaveunconnectedforclockinput.
REF
I
Input clock. Connect to X2 if crystal oscillator is used.
Q[1:3]
O
Output at N*REF frequency
Q0
O
OutputatN*REFinternallyconnectedforPLLfeedback
VDDQ
PWR
Powersupplyforthedeviceoutputs. ConnecttoVDDonPCB.
VDD
PWR
Powersupplyforthedevicecoreandinputs. ConnecttoVDD
on PCB.
GND
PWR
Groundsupply
NOTES:
1. H = HIGH
M = MEDIUM
L = LOW
2. Test mode for low frequency testing. In this mode, REF clock bypasses the VCO (VCO powered down) and the crystal oscillator is powered down.
DIVIDE SELECTION TABLE(1)
S1
S0
Divide-by-N Value
Mode
L
L
2
PLL
L
M
3
PLL
L
H
4
PLL
M
L
4.25
PLL
M
M
5
PLL
M
H
6
PLL
H
L
6.25
PLL
H
M
8
PLL
H
H
TEST
TEST(2)



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