전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

LPC47M192 데이터시트(PDF) 39 Page - SMSC Corporation

부품명 LPC47M192
상세설명  LPC SUPER I/O WITH HARDWARE MONITORING BLOCK
PDF  228 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  SMSC [SMSC Corporation]
홈페이지  http://www.smsc.com
Logo SMSC - SMSC Corporation

LPC47M192 데이터시트(HTML) 39 Page - SMSC Corporation

Back Button LPC47M192 Datasheet HTML 35Page - SMSC Corporation LPC47M192 Datasheet HTML 36Page - SMSC Corporation LPC47M192 Datasheet HTML 37Page - SMSC Corporation LPC47M192 Datasheet HTML 38Page - SMSC Corporation LPC47M192 Datasheet HTML 39Page - SMSC Corporation LPC47M192 Datasheet HTML 40Page - SMSC Corporation LPC47M192 Datasheet HTML 41Page - SMSC Corporation LPC47M192 Datasheet HTML 42Page - SMSC Corporation LPC47M192 Datasheet HTML 43Page - SMSC Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 39 / 228 page
background image
SMSC DS – LPC47M192
Page 39
Rev. 03/30/05
DATASHEET
Table 11 – FIFO Service Delay
FIFO THRESHOLD
EXAMPLES
MAXIMUM DELAY TO SERVICING AT
2 Mbps DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 4 us - 1.5 us = 2.5 us
2 x 4 us - 1.5 us = 6.5 us
8 x 4 us - 1.5 us = 30.5 us
15 x 4 us - 1.5 us = 58.5 us
FIFO THRESHOLD
EXAMPLES
MAXIMUM DELAY TO SERVICING AT
1 Mbps DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 8 us - 1.5 us = 6.5 us
2 x 8 us - 1.5 us = 14.5 us
8 x 8 us - 1.5 us = 62.5 us
15 x 8 us - 1.5 us = 118.5 us
FIFO THRESHOLD
EXAMPLES
MAXIMUM DELAY TO SERVICING AT
500 Kbps DATA RATE
1 byte
2 bytes
8 bytes
15 bytes
1 x 16 us - 1.5 us = 14.5 us
2 x 16 us - 1.5 us = 30.5 us
8 x 16 us - 1.5 us = 126.5 us
15 x 16 us - 1.5 us = 238.5 us
DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
7
6
5
4
3
2
1
0
DSK
CHG
0
0
0
0
0
0
0
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
BIT 0 – 6 UNDEFINED
The data bus outputs D0 – 6 are read as ‘0’.
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
PS/2 Mode
7
6
5
4
3
2
1
0
DSK
CHG
1
1
1
1
DRATE
SEL1
DRATE
SEL0
nHIGH
DENS
RESET
COND.
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are
selected.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com