AM652X datasheet(244/299 Pages) TI1

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244

AM6548, AM6528, AM6546

AM6526, AM6527

SPRSP08E – NOVEMBER 2017 – REVISED OCTOBER 2018

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Product Folder Links: AM6548 AM6528 AM6546 AM6526 AM6527

Detailed Description

For more information, see section Graphics Accelerator (GPU) in chapter Processors and Accelerators of

the device TRM.

6.6

PRU-ICSSG

The Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem (PRU_ICSSG)

consists of:

•

Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1)

•

Two Real-Time Transfer Units (RTU_PRU0 and RTU_PRU1)

•

Data RAMs per PRU core

•

Instruction RAMs per PRU and per RTU_PRU cores

•

Shared RAM

•

Peripheral modules

•

Interrupt controller (INTC)

The programmable nature of the PRU cores, along with their access to pins, events and all device

resources, provides flexibility in implementing fast real-time responses, specialized data handling

operations, custom peripheral interfaces, and in offloading tasks from the other processor cores of the

device.

The PRU cores are programmed with a small, deterministic instruction set. Each PRU can operate

independently or in coordination with each other and can also work in coordination with the device-level

host CPU. This interaction between processors is determined by the nature of the firmware loaded into the

PRU’s instruction memory.

The device has integrated three identical PRU_ICSSG subsystems (PRU_ICSSG0, PRU_ICSSG1 and

PRU_ICSSG2 ).

The PRU_ICSSG subsystem includes the following main features:

•

20 Enhanced General-Purpose Inputs (EGPI) and 20 Enhanced General-Purpose Outputs (EGPO)

•

Asynchronous capture [Serial Capture Unit (SCU)] with EnDat 2.2 protocol and Sigma-Delta

demodulation support

•

Two 32-bit load/store RISC CPU cores — Programmable Real-Time Units (PRU0 and PRU1), each

with

–

12KB program memory per PRU CPU (signified PRU0_IRAM for PRU0 and PRU1_IRAM for

PRU1) with ECC

–

4KB Broadside (BS) RAM

–

MAC (Multiplier with optional Accumulation)

–

CRC16/32 HW accelerator

–

Byte Swap, for Little/Big Endian conversion

–

SUM32 for UDP checksum

–

Task Manager

–

Supports 128-bit wide PSI-L TX port for streaming access to NAVSS0

–

Broadside (32-bit) connection to MII_G_RTn (where n= 1 or 2), Filter Data Base (FDB), Scratchpad

Memory (SPAD), SPINLOCK, XFR2VBUS, and RTU_PRUm (where m= 0 or 1)

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