LTC2412IGN datasheet(16/36 Pages) LINER

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LTC2412

2412f

APPLICATIO S I FOR ATIO

outside specifications but the following conversions will

not be affected. If the change occurs during the data output

state and the converter is in the Internal SCK mode, the

serial clock duty cycle may be affected but the serial data

stream will remain valid.

Table 3 summarizes the duration of each state and the

achievable output data rate as a function of FO.

SERIAL INTERFACE PINS

The LTC2412 transmits the conversion results and re-

ceives the start of conversion command through a syn-

chronous 3-wire interface. During the conversion and

sleep states, this interface can be used to assess the

converter status and during the data output state it is used

to read the conversion result.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 13) is used to

synchronize the data transfer. Each bit of data is shifted out

the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2412 creates its own serial clock by

dividing the internal conversion clock by 8. In the External

SCK mode of operation, the SCK pin is used as input. The

internal or external SCK mode is selected on power-up and

then reselected every time a HIGH-to-LOW transition is

detected at the CS pin. If SCK is HIGH or floating at power-

up or during this transition, the converter enters the inter-

nal SCK mode. If SCK is LOW at power-up or during this

transition, the converter enters the external SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 12), provides the

result of the last conversion as a serial bit stream (MSB

first) during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the

conversion and sleep states.

When CS (Pin 11) is HIGH, the SDO driver is switched to

a high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

during the conversion phase, the EOC bit appears HIGH on

the SDO pin. Once the conversion is complete, EOC goes

LOW.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 11), is used to test the

conversion status and to enable the data output transfer as

described in the previous sections.

In addition, the CS signal can be used to trigger a new

conversion cycle before the entire serial data transfer has

been completed. The LTC2412 will abort any serial data

transfer in progress and start a new conversion cycle

Table 3. LTC2412 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

FO = LOW

133ms, Output Data Rate

≤ 7.5 Readings/s

(60Hz Rejection)

FO = HIGH

160ms, Output Data Rate

≤ 6.2 Readings/s

(50Hz Rejection)

External Oscillator

FO = External Oscillator

20510/fEOSCs, Output Data Rate ≤ fEOSC/20510 Readings/s

with Frequency fEOSC kHz

(fEOSC/2560 Rejection)

SLEEP

As Long As CS = HIGH

DATA OUTPUT

Internal Serial Clock

FO = LOW/HIGH

As Long As CS = LOW But Not Longer Than 1.67ms

(Internal Oscillator)

(32 SCK cycles)

FO = External Oscillator with

As Long As CS = LOW But Not Longer Than 256/fEOSCms

Frequency fEOSC kHz

(32 SCK cycles)

External Serial Clock with

As Long As CS = LOW But Not Longer Than 32/fSCKms

Frequency fSCK kHz

(32 SCK cycles)

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