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ICS342 데이터시트(PDF) 1 Page - Integrated Device Technology

부품명 ICS342
상세설명  FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
PDF  9 Pages
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제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS342 데이터시트(HTML) 1 Page - Integrated Device Technology

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DATASHEET
FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER
I CS3 4 2
IDT® / ICS™ FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER 1
ICS342
REV N 090613
Description
The ICS342 is a low cost, dual-output, field programmable
clock synthesizer. The ICS342 can generate two output
frequencies from 250 kHz to 200 MHz, using up to two
independently configurable PLLs. The outputs may employ
Spread Spectrum techniques to reduce system
electro-magnetic interference (EMI).
Using IDT’s VersaClockTM software to configure the PLL
and output, the ICS342 contains a One-Time
Programmable (OTP) ROM to allow field programmability.
Programming features include 2 selectable configuration
registers. Using Phase-Locked Loop (PLL) techniques, the
device runs from a standard fundamental mode,
inexpensive crystal, or clock. It can replace multiple crystals
and oscillators, saving board space and cost.
The device also has a power down feature that tri-states the
clock outputs and turns off the PLLs when the PDTS pin is
taken low.
The ICS342 is also available in factory programmed custom
versions for high-volume applications.
Features
• 8-pin SOIC package (Pb-free)
• Highly accurate frequency generation
• M/N Multiplier PLL: M = 1...2048, N = 1...1024
• Output clock frequencies up to 200 MHz
• Two ROM locations for frequency and spread selection
• Spread spectrum capability for lower system EMI
• Center or Down Spread up to 4% total
• Selectable 32 kHz or 120 kHz modulation
• Input crystal frequency from 5 to 27 MHz
• Input clock frequency from 2 to 50 MHz
• Operating voltage of 3.3 V
• Advanced, low power CMOS process
• For one output clock, use the ICS341. For three output
clocks, see the ICS343. For more than three outputs, see
the ICS345 or ICS348.
Block Diagram
Crystal
Oscillator
PDTS (both outputs and PLL)
OTP ROM
with PLL
Divider
Values
SEL
VDD
GND
CLK1
CLK2
PLL Clock Synthesis,
Spred Spectrum and
Control Circuitry
X2
Crystal or
clock input
External capacitors are
required with a crystal input.
X1/ICLK


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