AD9152-EBZ datasheet(13/103 Pages) AD

13 / 103 page

Data Sheet

AD9152

Rev. B | Page 13 of 103

Pin No.

Mnemonic

Description

SVDD12

1.2 V JESD204B Rx Analog Supply.

SERDIN2−

Serial Channel Input 2, Negative. CML compliant. SERDIN2− is 50 Ω terminated to the VTT pin voltage. This

pin is ac-coupled only. Resistance calibrated

SERDIN2+

Serial Channel Input 2, Positive. CML compliant. SERDIN2+ is 50 Ω terminated to the VTT pin voltage. This pin

is ac-coupled only. Resistance calibrated.

SVDD12

1.2 V JESD204B Rx Analog Supply.

SERDIN3−

Serial Channel Input 3, Negative. CML compliant. SERDIN3− is 50 Ω terminated to the VTT pin voltage. This

pin is ac-coupled only. Resistance calibrated.

SERDIN3+

Serial Channel Input 3, Positive. CML compliant. SERDIN3+ is 50 Ω terminated to the VTT pin voltage. This pin

is ac-coupled only. Resistance calibrated.

SDVDD12

1.2 V JESD204B Rx Digital Supply.

VTT

1.2 V Termination Voltage. Connect VTT to the SVDD12 pin externally.

SVDD12

1.2 V JESD204B Rx Analog Supply.

SIOVDD33

3.3 V Supply for Equalizers.

SYNCOUT−

Negative LVDS Sync Output Signal.

SYNCOUT+

Positive LVDS Sync Output Signal.

DVDD12

1.2 V Digital Supply.

DVDD12

1.2 V Digital Supply.

PROTECT_OUT

Protection Indicator for I DAC and Q DAC. CMOS levels are determined with respect to IOVDD.

SDO

Serial Port Data Output. CMOS levels are determined with respect to IOVDD.

SDIO

Serial Port Data Input/Output. CMOS levels are determined with respect to IOVDD.

SCLK

Serial Port Clock Input. CMOS levels are determined with respect to IOVDD.

Serial Port Chip Select, Active Low. CMOS levels are determined with respect to IOVDD.

IOVDD

1.8 V IOVDD Supply for CMOS Input/Output and SPI.

AVDD33

3.3 V Analog Supply for the DAC Cores.

QOUT+

Q DAC Positive Current Output.

QOUT−

Q DAC Negative Current Output.

AVDD33

3.3 V Analog Supply for the DAC Cores.

CVDD12

1.2 V Clock Supply.

DACCLK+

Positive Device Clock When PLL Is Not Used.

DACCLK−

Negative Device Clock When PLL Is Not Used.

CVDD12

1.2 V Clock Supply.

AVDD33

3.3 V Analog Supply for the DAC Cores.

IOUT−

I DAC Negative Current Output.

IOUT+

I DAC Positive Current Output.

AVDD33

3.3 V Analog Supply for the DAC Cores.

I120

Output Current Generation Pin for the DAC Full-Scale Current. Tie a 4 kΩ resistor from this pin to the ground

plane.

CVDD12

1.2 V Clock Supply.

EPAD

Exposed Pad. The exposed pad must be securely connected to the ground plane.

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