UB264BL-AD-P08-R datasheet(7/11 Pages) UTC

7 / 11 page

UB264B

Preliminary

CMOS IC

UNISONICTECHNOLOGIESCO.,LTD

7 of 11

www.unisonic.com.tw

QW-R502-833.b



OPERATING(Cont.)

Notes:

The reverse voltage “H” to “L” or “L” to “H” of CTL pin is VDD pin voltage −2.8 V (Typ.), does not have

the hysteresis.

Since the CTL pin implements high resistance of 8MΩ to 12MΩ for pull down, be careful of external

noise application. If an external noise is applied, CO may become “H”. Perform thorough evaluation

using the actual application.

In the UTC UB264B Series, when the CTL pin is open or “L”, CO latches “H”. When the VDD pin

voltage is decreased to the UVLO voltage of 2 V (Typ.) or lower, the latch is reset.

4. Test Mode

In the UTC UB264B Series, the overcharge detection delay time (tCU) can be shortened by entering the test mode.

The test mode can be set by retaining the VDD pin voltage 8.5 V or more higher than the SENSE pin voltage for at

least 80ms (V1=V2=V3=V4=3.5 V, Ta=25°C). The status is retained by the internal latch and the test mode is

retained even if the VDD pin voltage is decreased to the same voltage as that of the SENSE pin. When CO becomes

“H” when the delay time has elapsed after overcharge detection, the latch for retaining the test mode is reset and the

UTC UB264B Series exits from the test mode.

tCU/64

CO Pin

Test mode

Battery voltage

(n=1 to 4)

VCUn

VHCn

Pin voltage

>8.5V

tTST

tCL

SENSE pin voltage

VDD pin voltage

Notes:

When the VDD pin voltage is decreased to lower than the UVLO voltage of 2 V (Typ.), the UTC

UB264B Series returns to the normal mode.

Set the test mode when no batteries are overcharged.

The overcharge release delay time (tCL) is not shortened in the test mode.

The overcharge timer reset delay time (tTR) is not shortened in the test mode.

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