AD9144BCPZ datasheet(14/125 Pages) AD

14 / 125 page

AD9144

Data Sheet

Rev. B | Page 14 of 125

Pin No.

Mnemonic

Description

SDO

Serial Port Data Output. CMOS levels are determined with respect to IOVDD.

SDIO

Serial Port Data Input/Output. CMOS levels are determined with respect to IOVDD.

SCLK

Serial Port Clock Input. CMOS levels are determined with respect to IOVDD.

Serial Port Chip Select. This pin is active low; CMOS levels are determined with respect to IOVDD.

IOVDD

IOVDD Supply for CMOS Input/Output and SPI. Operational for 1.8 V ≤ IOVDD ≤ 3.3 V.

AVDD33

3.3 V Analog Supply for DAC Cores.

OUT3+

DAC3 Positive Current Output.

OUT3−

DAC3 Negative Current Output.

LDO24

2.4 V LDO. Requires a 1 µF capacitor to ground.

CVDD12

1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 71.

LDO24

2.4 V LDO. Requires a 1 µF capacitor to ground.

OUT2−

DAC2 Negative Current Output.

OUT2+

DAC2 Positive Current Output.

AVDD33

3.3 V Analog Supply for DAC Cores.

CVDD12

1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 76.

AVDD33

3.3 V Analog Supply for DAC Cores.

OUT1+

DAC1 Positive Current Output.

OUT1−

DAC1 Negative Current Output.

LDO24

2.4 V LDO. Requires a 1 µF capacitor to ground.

CVDD12

1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 81.

LDO24

2.4 V LDO. Requires a 1 µF capacitor to ground.

OUT0−

DAC0 Negative Current Output.

OUT0+

DAC0 Positive Current Output.

AVDD33

3.3 V Analog Supply for DAC Cores.

I120

Output Current Generation Pin for DAC Full-Scale Current. Tie a 4 kΩ resistor from the I120 pin to ground.

CVDD12

1.2 V Clock Supply. Place bypass capacitors as near as possible to Pin 87.

LDO_BYP2

LDO Clock Bypass for DAC PLL. This pin requires a 1 Ω resistor in series with a 1 µF capacitor to ground.

EPAD

Exposed Pad. The exposed pad must be securely connected to the ground plane.

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